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Message-ID: <03048338-449d-6d4b-dfa9-d4eccba5cabb@quicinc.com>
Date: Tue, 6 Dec 2022 21:57:17 +0530
From: Sai Prakash Ranjan <quic_saipraka@...cinc.com>
To: Abel Vesa <abel.vesa@...aro.org>, Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Neil Armstrong <neil.armstrong@...aro.org>
CC: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>
Subject: Re: [PATCH v6 02/10] arm64: dts: qcom: Add base SM8550 dtsi
Hi Abel,
On 12/6/2022 6:42 PM, Abel Vesa wrote:
> Add base dtsi for SM8550 SoC and includes base description of
> CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved
> memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq,
> interconnect, thermal sensor, cpu cooling maps and SMMU nodes
> which helps boot to shell with console on boards with this SoC.
>
> Co-developed-by: Neil Armstrong <neil.armstrong@...aro.org>
> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
>
> Changes since v5:
> * changed the include of qcom,sm8550-tcsrcc.h to qcom,sm8550-tcsr.h
>
<snip>...
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
This should be IRQ_TYPE_LEVEL_LOW
> +
> + intc: interrupt-controller@...00000 {
> + compatible = "arm,gic-v3";
> + reg = <0 0x17100000 0 0x10000>, /* GICD */
> + <0 0x17180000 0 0x200000>; /* GICR * 8 */
> + ranges;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + #redistributor-regions = <1>;
> + redistributor-stride = <0 0x40000>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
And here as well, IRQ_TYPE_LEVEL_LOW
With these 2 corrections,
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@...cinc.com>
Thanks,
Sai
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