linux-kernel - Re: [PATCH 1/3] dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx

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Message-ID: <34fe4161718e395f5e9890f9358a25f697af9e24.camel@icenowy.me>
Date:   Wed, 07 Dec 2022 18:47:26 +0800
From:   Icenowy Zheng <uwu@...nowy.me>
To:     Marc Zyngier <maz@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Jisheng Zhang <jszhang@...nel.org>,
        Samuel Holland <samuel@...lland.org>
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org
Subject: Re: [PATCH 1/3] dt-bindings: timer: sifive,clint: add comaptibles
 for T-Head's C9xx

在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道：
> T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
> compliant to the newcoming ACLINT spec) because of lack of mtime
> register.
> 
> Add a compatible string formatted like the C9xx-specific PLIC
> compatible, and do not allow a SiFive one as fallback because they're
> not really compliant.
> 
> Signed-off-by: Icenowy Zheng <uwu@...nowy.me>

Hi, could this patch be picked ASAP? Becuase it will be used then in
further OpenSBI patches to enable proper operation of T-Head timer.

I know the following 2 patches are in doubt and further rework for them
are needed.

> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8
> ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index bbad24165837..aada6957216c 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -20,6 +20,10 @@ description:
>    property of "/cpus" DT node. The "timebase-frequency" DT property
> is
>    described in Documentation/devicetree/bindings/riscv/cpus.yaml
>  
> +  T-Head C906/C910 CPU cores include an implementation of CLINT too,
> however
> +  their implementation lacks a memory-mapped MTIME register, thus
> not
> +  compatible with SiFive ones.
> +
>  properties:
>    compatible:
>      oneOf:
> @@ -29,6 +33,10 @@ properties:
>                - starfive,jh7100-clint
>                - canaan,k210-clint
>            - const: sifive,clint0
> +      - items:
> +          - enum:
> +              - allwinner,sun20i-d1-clint
> +          - const: thead,c900-clint
>        - items:
>            - const: sifive,clint0
>            - const: riscv,clint0