linux-kernel - Re: [PATCH] cxl/region: Fix memdev reuse check

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Date:   Thu, 8 Dec 2022 13:22:04 -0800
From:   Dan Williams <dan.j.williams@...el.com>
To:     Fan Ni <fan.ni@...sung.com>,
        Dan Williams <dan.j.williams@...el.com>
CC:     "alison.schofield@...el.com" <alison.schofield@...el.com>,
        "vishal.l.verma@...el.com" <vishal.l.verma@...el.com>,
        "ira.weiny@...el.com" <ira.weiny@...el.com>,
        "bwidawsk@...nel.org" <bwidawsk@...nel.org>,
        "Jonathan.Cameron@...wei.com" <Jonathan.Cameron@...wei.com>,
        "dan.carpenter@...cle.com" <dan.carpenter@...cle.com>,
        "linux-cxl@...r.kernel.org" <linux-cxl@...r.kernel.org>,
        Adam Manzanares <a.manzanares@...sung.com>,
        "dave@...olabs.net" <dave@...olabs.net>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] cxl/region: Fix memdev reuse check

Fan Ni wrote:
> On Mon, Nov 07, 2022 at 03:40:36PM -0800, Dan Williams wrote:
> 
> > Fan Ni wrote:
> > > Memdev reuse in a region currently does not iterate over all of the
> > > interleave targets. Fix this by using existing iterator for memdev reuse
> > > check.
> > 
> > Not enough detail, what does this actually fix in practice? For example,
> > if an end user encountered this bug, what would they see as the
> > symptoms?  I could probably figure out, but for bugs I should not have
> > to, and more importantly downstream OSV kernel maintainers, who do not
> > have the same context as CXL developers, also need that information to
> > decide if this is a fix they want to backport into their kernel.
> > 
> 
> Hi Dan,
> Thanks for the feedback. Here are more details about the patch, and
> I will refine the patch.
> 
> cxlmd_target = cxled_to_memdev(cxled_target);
> if (cxlmd_target == cxlmd) {
> 	dev_dbg(&cxlr->dev,
> 			"%s already specified at position %d via: %s\n",
> 			dev_name(&cxlmd->dev), pos,
> 			dev_name(&cxled_target->cxld.dev));
> 	return -EBUSY;
> }
> 
> Before the patch, the check of whether or not a memdev has already been
> used as a target for the region (above code piece) will always be skipped.
> Given a memdev with more than one HDM decoder, an interleaved region can be
> created that maps multiple HPAs to the same DPA. According to CXL spec 3.0
> 8.1.3.8.4, "Aliasing (mapping more than one Host Physical Address (HPA) to a
> single Device Physical Address) is forbidden."
> 
> The CXL specification allows a device to have more than one HDM decoder
> ("The number of decoders implemented by a component are enumerated via the CXL
>  HDM Decoder Capability register (see Section 8.2.4.19.1"). If a CXL device
>  has multiple HDM decoders the current code allows to create memory regions
>  that map multiple HPAs to a single DPA.
> 
> Fan

Thanks for this explanation I folded this into the changelog and applied
it for v6.2.