lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3480FA50-B88E-4BD9-8E9F-27F231C2BAC6@kernel.org>
Date:   Thu, 08 Dec 2022 10:10:49 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Samuel Holland <samuel@...lland.org>, Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        linux-sunxi@...ts.linux.dev, Palmer Dabbelt <palmer@...belt.com>,
        linux-riscv@...ts.infradead.org
CC:     Jisheng Zhang <jszhang@...nel.org>, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Heiko Stuebner <heiko@...ech.de>,
        linux-arm-kernel@...ts.infradead.org,
        Andre Przywara <andre.przywara@....com>,
        Palmer Dabbelt <palmer@...osinc.com>,
        Guo Ren <guoren@...nel.org>
Subject: Re: [PATCH v3 11/12] riscv: Add the Allwinner SoC family Kconfig option

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

On 8 December 2022 10:02:36 GMT+01:00, Samuel Holland <samuel@...lland.org> wrote:
>Allwinner manufactures the sunxi family of application processors. This
>includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
>SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
>
>The first SoC in the sun20i series is D1, containing a single T-HEAD
>C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
>
>Most peripherals are shared across the entire chip family. In fact, the
>ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
>with the D1s.
>
>This means many existing device drivers can be reused. To facilitate
>this reuse, name the symbol ARCH_SUNXI, since that is what the existing
>drivers have as their dependency.
>
>Acked-by: Palmer Dabbelt <palmer@...osinc.com>
>Reviewed-by: Guo Ren <guoren@...nel.org>
>Reviewed-by: Heiko Stuebner <heiko@...ech.de>
>Tested-by: Heiko Stuebner <heiko@...ech.de>
>Signed-off-by: Samuel Holland <samuel@...lland.org>
>---
>
>Changes in v3:
> - ARCH_SUNXI depends on MMU && !XIP_KERNEL
>
>Changes in v2:
> - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing
>
> arch/riscv/Kconfig.socs | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
>diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>index 69774bb362d6..f655dea86d69 100644
>--- a/arch/riscv/Kconfig.socs
>+++ b/arch/riscv/Kconfig.socs
>@@ -26,6 +26,16 @@ config SOC_STARFIVE
> 	help
> 	  This enables support for StarFive SoC platform hardware.
> 
>+config ARCH_SUNXI
>+	bool "Allwinner sun20i SoCs"
>+	depends on MMU && !XIP_KERNEL
>+	select ERRATA_THEAD
>+	select SIFIVE_PLIC
>+	select SUN4I_TIMER
>+	help
>+	  This enables support for Allwinner sun20i platform hardware,
>+	  including boards based on the D1 and D1s SoCs.
>+
> config SOC_VIRT
> 	bool "QEMU Virt Machine"
> 	select CLINT_TIMER if RISCV_M_MODE

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ