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Message-ID: <Y5IAi/fgbJk1/h2L@zn.tnic>
Date: Thu, 8 Dec 2022 16:19:39 +0100
From: Borislav Petkov <bp@...en8.de>
To: linux-kernel@...r.kernel.org,
Linus Torvalds <torvalds@...ux-foundation.org>
Cc: linux-tip-commits@...r.kernel.org,
Ravi Bangoria <ravi.bangoria@....com>,
"Peter Zijlstra (Intel)" <peterz@...radead.org>,
Ian Rogers <irogers@...gle.com>, x86@...nel.org
Subject: Re: [tip: perf/core] perf/amd/ibs: Make IBS a core pmu
I believe this is one of the things Linus wanted to have on AMD hw.
On Thu, Nov 24, 2022 at 12:03:03PM -0000, tip-bot2 for Ravi Bangoria wrote:
> The following commit has been merged into the perf/core branch of tip:
>
> Commit-ID: 30093056f7b2f759ff180d3a86d29f68315e469b
> Gitweb: https://git.kernel.org/tip/30093056f7b2f759ff180d3a86d29f68315e469b
> Author: Ravi Bangoria <ravi.bangoria@....com>
> AuthorDate: Tue, 15 Nov 2022 15:09:04 +05:30
> Committer: Peter Zijlstra <peterz@...radead.org>
> CommitterDate: Thu, 24 Nov 2022 11:09:19 +01:00
>
> perf/amd/ibs: Make IBS a core pmu
>
> So far, only one pmu was allowed to be registered as core pmu and thus
> IBS pmus were being registered as uncore. However, with the event context
> rewrite, that limitation no longer exists and thus IBS pmus can also be
> registered as core pmu. This makes IBS much more usable, for ex, user
> will be able to do per-process precise monitoring on AMD:
>
> Before patch:
> $ sudo perf record -e cycles:pp ls
> Error:
> Invalid event (cycles:pp) in per-thread mode, enable system wide with '-a'
>
> After patch:
> $ sudo perf record -e cycles:pp ls
> [ perf record: Woken up 1 times to write data ]
> [ perf record: Captured and wrote 0.017 MB perf.data (33 samples) ]
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@....com>
> Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
> Acked-by: Ian Rogers <irogers@...gle.com>
> Link: https://lkml.kernel.org/r/20221115093904.1799-1-ravi.bangoria@amd.com
> ---
> arch/x86/events/amd/ibs.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
> index 3271735..fbc2ce8 100644
> --- a/arch/x86/events/amd/ibs.c
> +++ b/arch/x86/events/amd/ibs.c
> @@ -631,7 +631,7 @@ static const struct attribute_group *op_attr_update[] = {
>
> static struct perf_ibs perf_ibs_fetch = {
> .pmu = {
> - .task_ctx_nr = perf_invalid_context,
> + .task_ctx_nr = perf_hw_context,
>
> .event_init = perf_ibs_init,
> .add = perf_ibs_add,
> @@ -655,7 +655,7 @@ static struct perf_ibs perf_ibs_fetch = {
>
> static struct perf_ibs perf_ibs_op = {
> .pmu = {
> - .task_ctx_nr = perf_invalid_context,
> + .task_ctx_nr = perf_hw_context,
>
> .event_init = perf_ibs_init,
> .add = perf_ibs_add,
--
Regards/Gruss,
Boris.
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