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Message-ID: <Y5MRp5rWmW8ib+9f@hovoldconsulting.com>
Date: Fri, 9 Dec 2022 11:44:55 +0100
From: Johan Hovold <johan@...nel.org>
To: Bjorn Andersson <quic_bjorande@...cinc.com>
Cc: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Kalyan Thota <quic_kalyant@...cinc.com>,
Jessica Zhang <quic_jesszhan@...cinc.com>,
Kuogee Hsieh <quic_khsieh@...cinc.com>,
Johan Hovold <johan+linaro@...nel.org>,
Sankeerth Billakanti <quic_sbillaka@...cinc.com>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 12/12] arm64: dts: qcom: sa8295-adp: Enable DP
instances
On Wed, Dec 07, 2022 at 02:00:12PM -0800, Bjorn Andersson wrote:
> From: Bjorn Andersson <bjorn.andersson@...aro.org>
>
> The SA8295P ADP has, among other interfaces, six MiniDP connectors which
> are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3.
>
> Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers,
> DP PHYs and link them all together.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> Signed-off-by: Bjorn Andersson <quic_bjorande@...cinc.com>
> ---
>
> Changes since v4:
> - None
>
> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 243 ++++++++++++++++++++++-
> 1 file changed, 241 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> index 6c29d7d757e0..d55c8c5304cc 100644
> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> +&mdss0_dp2 {
> + status = "okay";
Please move 'status' last.
> +
> + data-lanes = <0 1 2 3>;
> +
> + ports {
> + port@1 {
> + reg = <1>;
> + mdss0_dp2_phy_out: endpoint {
> + remote-endpoint = <&edp0_connector_in>;
> + };
> + };
> + };
> +};
> +
> +&mdss0_dp2_phy {
> + status = "okay";
Same here.
> +
> + vdda-phy-supply = <&vreg_l8g>;
> + vdda-pll-supply = <&vreg_l3g>;
> +};
> +
> +&mdss0_dp3 {
> + status = "okay";
And here.
> +
> + data-lanes = <0 1 2 3>;
> +
> + ports {
> + port@1 {
> + reg = <1>;
> + mdss0_dp3_phy_out: endpoint {
> + remote-endpoint = <&edp1_connector_in>;
> + };
> + };
> + };
> +};
> +
> +&mdss0_dp3_phy {
> + status = "okay";
And here.
> +
> + vdda-phy-supply = <&vreg_l8g>;
> + vdda-pll-supply = <&vreg_l3g>;
> +};
> +
> +&mdss1 {
> + status = "okay";
> +};
> +
> +&mdss1_dp0 {
> + status = "okay";
And here.
> +
> + data-lanes = <0 1 2 3>;
> +
> + ports {
> + port@1 {
> + reg = <1>;
> + mdss1_dp0_phy_out: endpoint {
> + remote-endpoint = <&dp2_connector_in>;
> + };
> + };
> + };
> +};
> +
> +&mdss1_dp0_phy {
> + status = "okay";
Ditto.
> +
> + vdda-phy-supply = <&vreg_l11g>;
> + vdda-pll-supply = <&vreg_l3g>;
> +};
> +
> +&mdss1_dp1 {
> + status = "okay";
Ditto.
> +
> + data-lanes = <0 1 2 3>;
> +
> + ports {
> + port@1 {
> + reg = <1>;
> + mdss1_dp1_phy_out: endpoint {
> + remote-endpoint = <&dp3_connector_in>;
> + };
> + };
> + };
> +};
> +
> +&mdss1_dp1_phy {
> + status = "okay";
Ditto.
> +
> + vdda-phy-supply = <&vreg_l11g>;
> + vdda-pll-supply = <&vreg_l3g>;
> +};
> +
> +&mdss1_dp2 {
> + status = "okay";
Ditto.
> +
> + data-lanes = <0 1 2 3>;
> +
> + ports {
> + port@1 {
> + reg = <1>;
> + mdss1_dp2_phy_out: endpoint {
> + remote-endpoint = <&edp2_connector_in>;
> + };
> + };
> + };
> +};
> +
> +&mdss1_dp2_phy {
> + status = "okay";
Ditto.
> +
> + vdda-phy-supply = <&vreg_l11g>;
> + vdda-pll-supply = <&vreg_l3g>;
> +};
> +
> +&mdss1_dp3 {
> + status = "okay";
Ditto.
> +
> + data-lanes = <0 1 2 3>;
> +
> + ports {
> + port@1 {
> + reg = <1>;
> + mdss1_dp3_phy_out: endpoint {
> + remote-endpoint = <&edp3_connector_in>;
> + };
> + };
> + };
> +};
> +
> +&mdss1_dp3_phy {
> + status = "okay";
Ditto.
> +
> + vdda-phy-supply = <&vreg_l11g>;
> + vdda-pll-supply = <&vreg_l3g>;
> +};
> +
> &pcie2a {
> perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
> wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
Johan
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