linux-kernel - [RFC 1/1] ARM: Drop !ARCH_MULTIPLATFORM dependency from Cortex A8/9 erratas

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Message-Id: <20221209182000.549179-1-sebastian.reichel@collabora.com>
Date:   Fri,  9 Dec 2022 19:20:00 +0100
From:   Sebastian Reichel <sebastian.reichel@...labora.com>
To:     Russell King <linux@...linux.org.uk>, Arnd Bergmann <arnd@...db.de>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Sebastian Reichel <sebastian.reichel@...labora.com>,
        kernel@...labora.com
Subject: [RFC 1/1] ARM: Drop !ARCH_MULTIPLATFORM dependency from Cortex A8/9 erratas

All the erratas for more recent CPUs (Cortex A15/A12/A17) do not
require !ARCH_MULTIPLATFORM, since there is runtime detection of
effected CPUs in arch/arm/mm/proc-v7.S.

Errata config options for the older Cortex A8/A9 CPUs have the
!ARCH_MULTIPLATFORM dependency, but the CPUs are also runtime
detected. Since there is runtime detection, it should be fine
to enable the erratas for a multi platform kernel.

Signed-off-by: Sebastian Reichel <sebastian.reichel@...labora.com>
---
For me the most likely explanation that this has not yet happened is
me missing an important detail, so I sent it as RFC. If you point it
out I will try to document the reason.
---
 arch/arm/Kconfig | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a08c9d092a33..fafb02e38507 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -647,7 +647,6 @@ config ARM_ERRATA_430973
 config ARM_ERRATA_458693
 	bool "ARM errata: Processor deadlock when a false hazard is created"
 	depends on CPU_V7
-	depends on !ARCH_MULTIPLATFORM
 	help
 	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 	  erratum. For very specific sequences of memory operations, it is
@@ -661,7 +660,6 @@ config ARM_ERRATA_458693
 config ARM_ERRATA_460075
 	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
 	depends on CPU_V7
-	depends on !ARCH_MULTIPLATFORM
 	help
 	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
 	  erratum. Any asynchronous access to the L2 cache may encounter a
@@ -674,7 +672,6 @@ config ARM_ERRATA_460075
 config ARM_ERRATA_742230
 	bool "ARM errata: DMB operation may be faulty"
 	depends on CPU_V7 && SMP
-	depends on !ARCH_MULTIPLATFORM
 	help
 	  This option enables the workaround for the 742230 Cortex-A9
 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
@@ -687,7 +684,6 @@ config ARM_ERRATA_742230
 config ARM_ERRATA_742231
 	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
 	depends on CPU_V7 && SMP
-	depends on !ARCH_MULTIPLATFORM
 	help
 	  This option enables the workaround for the 742231 Cortex-A9
 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
@@ -725,7 +721,6 @@ config ARM_ERRATA_720789
 config ARM_ERRATA_743622
 	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
 	depends on CPU_V7
-	depends on !ARCH_MULTIPLATFORM
 	help
 	  This option enables the workaround for the 743622 Cortex-A9
 	  (r2p*) erratum. Under very rare conditions, a faulty
@@ -739,7 +734,6 @@ config ARM_ERRATA_743622
 config ARM_ERRATA_751472
 	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
 	depends on CPU_V7
-	depends on !ARCH_MULTIPLATFORM
 	help
 	  This option enables the workaround for the 751472 Cortex-A9 (prior
 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
-- 
2.38.1