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Message-ID: <PH7PR11MB595857123B23F27D1E9DE2D39B1F9@PH7PR11MB5958.namprd11.prod.outlook.com>
Date: Sat, 10 Dec 2022 11:19:18 +0000
From: <Tharunkumar.Pasumarthi@...rochip.com>
To: <andriy.shevchenko@...ux.intel.com>,
<Kumaravel.Thiagarajan@...rochip.com>
CC: <linux-kernel@...r.kernel.org>, <linux-serial@...r.kernel.org>,
<gregkh@...uxfoundation.org>, <jirislaby@...nel.org>,
<ilpo.jarvinen@...ux.intel.com>, <macro@...am.me.uk>,
<cang1@...e.co.uk>, <colin.i.king@...il.com>,
<phil.edworthy@...esas.com>, <biju.das.jz@...renesas.com>,
<geert+renesas@...der.be>, <lukas@...ner.de>,
<u.kleine-koenig@...gutronix.de>, <wander@...hat.com>,
<etremblay@...tech-controls.com>, <jk@...abs.org>
Subject: RE: [PATCH v7 tty-next 2/4] serial: 8250_pci1xxxx: Add driver for
quad-uart support
> From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> Sent: Thursday, December 8, 2022 1:31 AM
> To: Kumaravel Thiagarajan - I21417
> <Kumaravel.Thiagarajan@...rochip.com>
> Subject: Re: [PATCH v7 tty-next 2/4] serial: 8250_pci1xxxx: Add driver for
> quad-uart support
>
> > + priv->membase = pcim_iomap(pdev, 0, 0);
>
> Is any of those card can have an IO bar (instead of MEM)?
No Andy
> > + if (num_vectors == 4)
> > + writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI,
> > + priv->membase + UART_PCI_CTRL_REG);
>
> If you set this unconditionally when num_vectors < 4, would it still work?
UART_PCI_CTRL_SET_MULTIPLE_MSI must be set only when all the requested interrupt vectors
are allocated by the pci_alloc_irq_vectors API. Number of interrupt vectors requested was always
4 previously and that logic will be modified to request only which is required in V8 patch.
Thanks,
Tharun Kumar P
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