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Date: Mon, 12 Dec 2022 13:59:41 +0000
From: Kenneth Sloat <ksloat@...ignlinxhs.com>
To: "sean.anderson@...o.com" <sean.anderson@...o.com>,
"michal.simek@...inx.com" <michal.simek@...inx.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Kenneth Sloat <ksloat@...ignlinxhs.com>
Subject: [PATCH] pwm: xilinx: Fix overflow issue in 32-bit width PWM mode.
This timer HW supports 8, 16 and 32-bit timer widths. This
driver uses a u32 to store the max value of the timer.
Because addition is done to this max value, when operating
in 32-bit mode, this will result in overflow that makes it
impossible to set the timer period and thus the PWM itself.
To fix this, simply make max a u64. This was tested on a
Zynq UltraScale+.
Signed-off-by: Ken Sloat <ksloat@...ignlinxhs.com>
---
include/clocksource/timer-xilinx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/clocksource/timer-xilinx.h b/include/clocksource/timer-xilinx.h
index c0f56fe6d22a..d116f18de899 100644
--- a/include/clocksource/timer-xilinx.h
+++ b/include/clocksource/timer-xilinx.h
@@ -41,7 +41,7 @@ struct regmap;
struct xilinx_timer_priv {
struct regmap *map;
struct clk *clk;
- u32 max;
+ u64 max;
};
/**
--
2.17.1
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