linux-kernel - Re: [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO

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Message-ID: <CA+V-a8tuCV-p-BR3nAKZ+4Z1GnRus8eEKJZ_sBaTaa2mjqBb1w@mail.gmail.com>
Date:   Tue, 13 Dec 2022 17:57:30 +0000
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Magnus Damm <magnus.damm@...il.com>,
        Heiko Stuebner <heiko@...ech.de>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Samuel Holland <samuel@...lland.org>,
        Guo Ren <guoren@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Jisheng Zhang <jszhang@...nel.org>,
        Atish Patra <atishp@...osinc.com>,
        Anup Patel <apatel@...tanamicro.com>,
        Andrew Jones <ajones@...tanamicro.com>,
        Nathan Chancellor <nathan@...nel.org>,
        Philipp Tomsich <philipp.tomsich@...ll.eu>,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-renesas-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
        Biju Das <biju.das.jz@...renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and
 operation to ALT_CMO_OP()

Hi Geert,

On Tue, Dec 13, 2022 at 5:15 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Dec 12, 2022 at 12:55 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Pass direction and operation to ALT_CMO_OP() macro.
> >
> > Vendors might want to perform different operations based on the direction
> > and callbacks (arch_sync_dma_for_device/arch_sync_dma_for_cpu/
> > arch_dma_prep_coherent) so to handle such cases pass the direction and
> > operation to ALT_CMO_OP() macro. This is in preparation for adding errata
> > for the Andes CPU core.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE(                                           \
> >  #define THEAD_flush_A0 ".long 0x0275000b"
> >  #define THEAD_SYNC_S   ".long 0x0190000b"
> >
> > -#define ALT_CMO_OP(_op, _start, _size, _cachesize)                     \
> > +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops)         \
>
> Since commit a49ab905a1fc8630 ("RISC-V: Implement arch specific PMEM
> APIs") in riscv/for-next, there are two new users of this macro,
> which need to be updated to (add two zeroes?).
>
Thanks for pointing that out, I'll rebase on for-next. I think -1
would be a better option than zeros.

Cheers,
Prabhakar