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Date: Tue, 13 Dec 2022 22:43:06 +0000 From: Fabrizio Castro <fabrizio.castro.jz@...esas.com> To: Linus Walleij <linus.walleij@...aro.org>, Bartosz Golaszewski <brgl@...ev.pl>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Sebastian Reichel <sre@...nel.org>, Geert Uytterhoeven <geert+renesas@...der.be> Cc: Fabrizio Castro <fabrizio.castro.jz@...esas.com>, Lee Jones <lee@...nel.org>, linux-gpio@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org, Chris Paterson <Chris.Paterson2@...esas.com>, Biju Das <biju.das@...renesas.com>, linux-renesas-soc@...r.kernel.org, Laurent Pinchart <laurent.pinchart@...asonboard.com>, Jacopo Mondi <jacopo@...ndi.org> Subject: [PATCH 1/5] dt-bindings: gpio: Add RZ/V2M PWC GPIO driver bindings Add dt-bindings document for the RZ/V2M PWC GPIO driver. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com> --- .../bindings/gpio/renesas,rzv2m-pwc-gpio.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml b/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml new file mode 100644 index 000000000000..ecc034d53259 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/renesas,rzv2m-pwc-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) GPIO + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with General-Purpose + Output pins, alongside the below functions + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + This node uses syscon to map the register used to control the GPIOs + (the register map is retrieved from the parent dt-node), and the node should + be represented as a sub node of a "syscon", "simple-mfd" node. + +maintainers: + - Fabrizio Castro <fabrizio.castro.jz@...esas.com> + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc-gpio # RZ/V2M + - renesas,r9a09g055-pwc-gpio # RZ/V2MA + - const: renesas,rzv2m-pwc-gpio + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Offset in the register map for controlling the GPIOs (in bytes). + + regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the register map node. + + gpio-controller: true + + '#gpio-cells': + const: 2 + +required: + - compatible + - regmap + - offset + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + gpio { + compatible = "renesas,r9a09g011-pwc-gpio", + "renesas,rzv2m-pwc-gpio"; + regmap = <®mapnode>; + offset = <0x80>; + gpio-controller; + #gpio-cells = <2>; + }; -- 2.34.1
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