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Date: Tue, 13 Dec 2022 12:46:18 +0530
From: Shazad Hussain <quic_shazhuss@...cinc.com>
To: Brian Masney <bmasney@...hat.com>, <andersson@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>
CC: <konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<johan+linaro@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<ahalaney@...hat.com>, <echanude@...hat.com>
Subject: Re: [PATCH 4/4] arm64: dts: qcom: sc8280xp: add missing spi nodes
On 12/12/2022 11:53 PM, Brian Masney wrote:
> Add the missing nodes for the spi buses that's present on this SoC.
>
> This work was derived from various patches that Qualcomm delivered
> to Red Hat in a downstream kernel.
>
> Signed-off-by: Brian Masney <bmasney@...hat.com>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 384 +++++++++++++++++++++++++
> 1 file changed, 384 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 392a1509f0be..b50db09feae2 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -829,6 +829,22 @@ qup2_i2c16: i2c@...000 {
> status = "disabled";
> };
>
> + qup2_spi16: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00880000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
> + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
This is device property not host and same applicable for all below spi
nodes.
Also FYI let's enable below SPI for Qdrive usecases once spidev
compatible name is confirmed.
SE9 0x00A84000
SE22 0x00898000
-Shazad
> + status = "disabled";
> + };
> +
> qup2_i2c17: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00884000 0 0x4000>;
> @@ -845,6 +861,22 @@ qup2_i2c17: i2c@...000 {
> status = "disabled";
> };
>
> + qup2_spi17: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00884000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
> + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup2_uart17: serial@...000 {
> compatible = "qcom,geni-uart";
> reg = <0 0x00884000 0 0x4000>;
> @@ -875,6 +907,22 @@ qup2_i2c18: i2c@...000 {
> status = "disabled";
> };
>
> + qup2_spi18: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00888000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
> + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup2_i2c19: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x0088c000 0 0x4000>;
> @@ -891,6 +939,22 @@ qup2_i2c19: i2c@...000 {
> status = "disabled";
> };
>
> + qup2_spi19: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x0088c000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
> + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup2_i2c20: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00890000 0 0x4000>;
> @@ -907,6 +971,22 @@ qup2_i2c20: i2c@...000 {
> status = "disabled";
> };
>
> + qup2_spi20: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00890000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
> + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup2_i2c21: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00894000 0 0x4000>;
> @@ -923,6 +1003,22 @@ qup2_i2c21: i2c@...000 {
> status = "disabled";
> };
>
> + qup2_spi21: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00894000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
> + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup2_i2c22: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00898000 0 0x4000>;
> @@ -939,6 +1035,22 @@ qup2_i2c22: i2c@...000 {
> status = "disabled";
> };
>
> + qup2_spi22: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00898000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
> + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup2_i2c23: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x0089c000 0 0x4000>;
> @@ -954,6 +1066,22 @@ qup2_i2c23: i2c@...000 {
> interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
> +
> + qup2_spi23: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x0089c000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
> + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> };
>
> qup0: geniqup@...000 {
> @@ -986,6 +1114,22 @@ qup0_i2c0: i2c@...000 {
> status = "disabled";
> };
>
> + qup0_spi0: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00980000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup0_i2c1: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00984000 0 0x4000>;
> @@ -1002,6 +1146,22 @@ qup0_i2c1: i2c@...000 {
> status = "disabled";
> };
>
> + qup0_spi1: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00984000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup0_i2c2: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00988000 0 0x4000>;
> @@ -1018,6 +1178,22 @@ qup0_i2c2: i2c@...000 {
> status = "disabled";
> };
>
> + qup0_spi2: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00988000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup0_i2c3: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x0098c000 0 0x4000>;
> @@ -1034,6 +1210,22 @@ qup0_i2c3: i2c@...000 {
> status = "disabled";
> };
>
> + qup0_spi3: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x0098c000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup0_i2c4: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00990000 0 0x4000>;
> @@ -1050,6 +1242,22 @@ qup0_i2c4: i2c@...000 {
> status = "disabled";
> };
>
> + qup0_spi4: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00990000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup0_i2c5: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00994000 0 0x4000>;
> @@ -1066,6 +1274,22 @@ qup0_i2c5: i2c@...000 {
> status = "disabled";
> };
>
> + qup0_spi5: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00994000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup0_i2c6: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00998000 0 0x4000>;
> @@ -1082,6 +1306,22 @@ qup0_i2c6: i2c@...000 {
> status = "disabled";
> };
>
> + qup0_spi6: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00998000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup0_i2c7: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x0099c000 0 0x4000>;
> @@ -1097,6 +1337,22 @@ qup0_i2c7: i2c@...000 {
> interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
> +
> + qup0_spi7: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x0099c000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
> + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> };
>
> qup1: geniqup@...000 {
> @@ -1129,6 +1385,22 @@ qup1_i2c8: i2c@...000 {
> status = "disabled";
> };
>
> + qup1_spi8: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00a80000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup1_i2c9: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00a84000 0 0x4000>;
> @@ -1145,6 +1417,22 @@ qup1_i2c9: i2c@...000 {
> status = "disabled";
> };
>
> + qup1_spi9: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00a84000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup1_i2c10: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00a88000 0 0x4000>;
> @@ -1161,6 +1449,22 @@ qup1_i2c10: i2c@...000 {
> status = "disabled";
> };
>
> + qup1_spi10: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00a88000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup1_i2c11: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00a8c000 0 0x4000>;
> @@ -1177,6 +1481,22 @@ qup1_i2c11: i2c@...000 {
> status = "disabled";
> };
>
> + qup1_spi11: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00a8c000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup1_i2c12: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00a90000 0 0x4000>;
> @@ -1193,6 +1513,22 @@ qup1_i2c12: i2c@...000 {
> status = "disabled";
> };
>
> + qup1_spi12: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00a90000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup1_i2c13: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00a94000 0 0x4000>;
> @@ -1209,6 +1545,22 @@ qup1_i2c13: i2c@...000 {
> status = "disabled";
> };
>
> + qup1_spi13: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00a94000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup1_i2c14: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00a98000 0 0x4000>;
> @@ -1225,6 +1577,22 @@ qup1_i2c14: i2c@...000 {
> status = "disabled";
> };
>
> + qup1_spi14: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00a98000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> +
> qup1_i2c15: i2c@...000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00a9c000 0 0x4000>;
> @@ -1240,6 +1608,22 @@ qup1_i2c15: i2c@...000 {
> interconnect-names = "qup-core", "qup-config", "qup-memory";
> status = "disabled";
> };
> +
> + qup1_spi15: spi@...000 {
> + compatible = "qcom,geni-spi";
> + reg = <0 0x00a9c000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + spi-max-frequency = <50000000>;
> + status = "disabled";
> + };
> };
>
> pcie4: pcie@...0000 {
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