linux-kernel - [PATCH 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap

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Date:   Tue, 13 Dec 2022 18:18:54 +0530
From:   Sinthu Raja <sinthu.raja@...tralsolutions.com>
To:     Vinod Koul <vkoul@...nel.org>,
        Ravi Gunasekaran <r-gunasekaran@...com>,
        Siddharth Vadapalli <s-vadapalli@...com>
Cc:     Vignesh Raghavendra <vigneshr@...com>,
        Roger Quadros <rogerq@...nel.org>,
        linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Sinthu Raja <sinthu.raja@...com>
Subject: [PATCH 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap

Serdes wiz supports both LN23 and LN10 Type-C swap. Add support to
configure LN23 bit to swap between lane2 or lane3 if required.

Signed-off-by: Sinthu Raja <sinthu.raja@...com>
---
 drivers/phy/ti/phy-j721e-wiz.c | 33 +++++++++++++++++++++++++++++----
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index b17eec632d49..0091892af0b0 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -58,6 +58,11 @@ enum wiz_lane_standard_mode {
 	LANE_MODE_GEN4,
 };
 
+enum wiz_lane_typec_swap_mode {
+	LANE10_SWAP = 0,
+	LANE23_SWAP = 2,
+};
+
 enum wiz_refclk_mux_sel {
 	PLL0_REFCLK,
 	PLL1_REFCLK,
@@ -194,6 +199,9 @@ static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
 static const struct reg_field typec_ln10_swap =
 					REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
 
+static const struct reg_field typec_ln23_swap =
+					REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
+
 struct wiz_clk_mux {
 	struct clk_hw		hw;
 	struct regmap_field	*field;
@@ -366,6 +374,7 @@ struct wiz {
 	struct regmap_field	*mux_sel_field[WIZ_MUX_NUM_CLOCKS];
 	struct regmap_field	*div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
 	struct regmap_field	*typec_ln10_swap;
+	struct regmap_field	*typec_ln23_swap;
 	struct regmap_field	*sup_legacy_clk_override;
 
 	struct device		*dev;
@@ -675,6 +684,13 @@ static int wiz_regfield_init(struct wiz *wiz)
 		return PTR_ERR(wiz->typec_ln10_swap);
 	}
 
+	wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
+						       typec_ln23_swap);
+	if (IS_ERR(wiz->typec_ln23_swap)) {
+		dev_err(dev, "LN23_SWAP reg field init failed\n");
+		return PTR_ERR(wiz->typec_ln23_swap);
+	}
+
 	wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
 	if (IS_ERR(wiz->phy_en_refclk)) {
 		dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
@@ -1242,15 +1258,24 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
 				regmap_field_write(wiz->typec_ln10_swap, 0);
 		} else {
 			/* if no typec-dir gpio was specified, and USB lines
-			 * are connected to Lane 0 then set LN10 SWAP bit to 1.
+			 * are connected to SWAP lanes '0' or '2' then set LN10 SWAP
+			 * or LN23 bit to 1 respectively.
 			 */
 			u32 num_lanes = wiz->num_lanes;
 			int i;
 
 			for (i = 0; i < num_lanes; i++) {
-				if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3) \
-						&& wiz->lane_phy_reg[i] == 0) {
-					regmap_field_write(wiz->typec_ln10_swap, 1);
+				if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
+					switch (wiz->lane_phy_reg[i]) {
+					case LANE10_SWAP:
+						regmap_field_write(wiz->typec_ln10_swap, 1);
+						break;
+					case LANE23_SWAP:
+						regmap_field_write(wiz->typec_ln23_swap, 1);
+						break;
+					default:
+						break;
+					}
 				}
 			}
 		}
-- 
2.36.1