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Message-ID: <aa692a69-fc8d-472e-e5ae-276c3d6d7d78@linaro.org>
Date: Tue, 13 Dec 2022 17:24:45 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
andersson@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, bp@...en8.de,
tony.luck@...el.com
Cc: quic_saipraka@...cinc.com, konrad.dybcio@...aro.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
james.morse@....com, mchehab@...nel.org, rric@...nel.org,
linux-edac@...r.kernel.org, quic_ppareek@...cinc.com,
luca.weiss@...rphone.com, stable@...r.kernel.org
Subject: Re: [PATCH v2 02/13] dt-bindings: arm: msm: Fix register regions used
for LLCC banks
On 12/12/2022 13:33, Manivannan Sadhasivam wrote:
> Register regions of the LLCC banks are located at separate addresses.
> Currently, the binding just lists the LLCC0 base address and specifies
> the size to cover all banks. This is not the correct approach since,
> there are holes and other registers located in between.
>
> So let's specify the base address of each LLCC bank and get rid of
> reg-names property as it is not needed anymore. It should be noted that
> the bank count differs for each SoC, so that also needs to be taken into
> account in the binding.
>
> Cc: <stable@...r.kernel.org> # 4.19
> Fixes: 7e5700ae64f6 ("dt-bindings: Documentation for qcom, llcc")
> Reported-by: Parikshit Pareek <quic_ppareek@...cinc.com>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
> .../bindings/arm/msm/qcom,llcc.yaml | 97 ++++++++++++++++---
> 1 file changed, 83 insertions(+), 14 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
> index d1df49ffcc1b..260bc87629a7 100644
> --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
> @@ -33,14 +33,8 @@ properties:
> - qcom,sm8550-llcc
>
> reg:
> - items:
> - - description: LLCC base register region
> - - description: LLCC broadcast base register region
> -
> - reg-names:
> - items:
> - - const: llcc_base
> - - const: llcc_broadcast_base
> + minItems: 2
> + maxItems: 9
>
> interrupts:
> maxItems: 1
> @@ -48,7 +42,76 @@ properties:
> required:
> - compatible
> - reg
> - - reg-names
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc7180-llcc
> + - qcom,sm6350-llcc
> + then:
> + properties:
> + reg:
> + items:
> + - description: LLCC0 base register region
> + - description: LLCC broadcast base register region
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc7280-llcc
> + then:
> + properties:
> + reg:
> + items:
> + - description: LLCC0 base register region
> + - description: LLCC1 base register region
> + - description: LLCC broadcast base register region
This will break all existing users (all systems, bootloaders/firmwares),
so you need to explain that in commit msg - why breaking is allowed, who
is or is not going to be affected etc. Otherwise judging purely by
bindings this is an ABI break.
Reason "This is not the correct approach since, there are holes and
other registers located in between." is not enough, because this
suggests previous approach was just not the best and you have something
better. Better is not a reason for ABI break.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc8180x-llcc
> + - qcom,sc8280xp-llcc
> + then:
> + properties:
> + reg:
> + items:
> + - description: LLCC0 base register region
> + - description: LLCC1 base register region
> + - description: LLCC2 base register region
> + - description: LLCC3 base register region
> + - description: LLCC4 base register region
> + - description: LLCC5 base register region
> + - description: LLCC6 base register region
> + - description: LLCC7 base register region
> + - description: LLCC broadcast base register region
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdm845-llcc
> + - qcom,sm8150-llcc
> + - qcom,sm8250-llcc
> + - qcom,sm8350-llcc
> + - qcom,sm8450-llcc
> + then:
> + properties:
> + reg:
> + items:
> + - description: LLCC0 base register region
> + - description: LLCC1 base register region
> + - description: LLCC2 base register region
> + - description: LLCC3 base register region
> + - description: LLCC broadcast base register region
>
> additionalProperties: false
>
> @@ -56,9 +119,15 @@ examples:
> - |
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> - system-cache-controller@...0000 {
> - compatible = "qcom,sdm845-llcc";
> - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
> - reg-names = "llcc_base", "llcc_broadcast_base";
> - interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + system-cache-controller@...0000 {
> + compatible = "qcom,sdm845-llcc";
Inconsistent indentation for DTS example. Use 4 spaces for it.
> + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
> + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
> + <0 0x01300000 0 0x50000>;
> + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
Best regards,
Krzysztof
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