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Message-ID: <Y5mEK+d4MRB/vmNI@pendragon.ideasonboard.com>
Date: Wed, 14 Dec 2022 10:07:07 +0200
From: Laurent Pinchart <laurent.pinchart@...asonboard.com>
To: Marcel Ziswiler <marcel@...wiler.com>
Cc: linux-arm-kernel@...ts.infradead.org,
Shawn Guo <shawnguo@...nel.org>,
NXP Linux Team <linux-imx@....com>,
Lucas Stach <l.stach@...gutronix.de>,
Richard Zhu <hongxing.zhu@....com>,
Marcel Ziswiler <marcel.ziswiler@...adex.com>,
Fabio Estevam <festevam@...il.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Max Krummenacher <max.krummenacher@...adex.com>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Philippe Schenker <philippe.schenker@...adex.com>,
Rob Herring <robh+dt@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] arm64: dts: verdin-imx8mp: add pcie support
Hi Marcel,
Thank you for your humble patch ;-)
On Wed, Dec 14, 2022 at 07:13:54AM +0100, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@...adex.com>
>
> Add PCIe support on the Verdin iMX8M Plus.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@...asonboard.com>
> ---
> This has successfully been tested with Lucas' imx8mp-hsio-blk-ctrl high
> performance PLL clock exposure patch set [1] a later version thereof
> hopefully may land together with my humble patch. Thanks!
>
> [1] https://lore.kernel.org/all/20221213160112.1900410-1-l.stach@pengutronix.de/
>
> .../dts/freescale/imx8mp-verdin-dahlia.dtsi | 9 +++++++-
> .../boot/dts/freescale/imx8mp-verdin.dtsi | 22 ++++++++++++++++++-
> 2 files changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> index 80db1ad7c230..56b0e4b865c9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
> @@ -67,7 +67,14 @@ &i2c4 {
> /* TODO: Audio Codec */
> };
>
> -/* TODO: Verdin PCIE_1 */
> +/* Verdin PCIE_1 */
> +&pcie {
> + status = "okay";
> +};
> +
> +&pcie_phy {
> + status = "okay";
> +};
>
> /* Verdin PWM_1 */
> &pwm1 {
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
> index 6a1890a4b5d8..f3a46f4caf49 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
> @@ -749,7 +749,27 @@ eeprom_carrier_board: eeprom@57 {
> };
> };
>
> -/* TODO: Verdin PCIE_1 */
> +/* Verdin PCIE_1 */
> +&pcie {
> + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> + assigned-clock-rates = <10000000>;
> + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> + <&clk IMX8MP_CLK_PCIE_ROOT>,
> + <&clk IMX8MP_CLK_HSIO_AXI>;
> + clock-names = "pcie", "pcie_aux", "pcie_bus";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + /* PCIE_1_RESET# (SODIMM 244) */
> + reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
> +};
> +
> +&pcie_phy {
> + clocks = <&hsio_blk_ctrl>;
> + clock-names = "ref";
> + fsl,clkreq-unsupported;
> + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
> +};
>
> /* Verdin PWM_1 */
> &pwm1 {
--
Regards,
Laurent Pinchart
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