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Message-ID: <Y5m3Lh0wte/HN9NH@smile.fi.intel.com>
Date:   Wed, 14 Dec 2022 13:44:46 +0200
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Hanna Hawa <hhhawa@...zon.com>
Cc:     jarkko.nikula@...ux.intel.com, mika.westerberg@...ux.intel.com,
        jsd@...ihalf.com, linux-i2c@...r.kernel.org,
        linux-kernel@...r.kernel.org, dwmw@...zon.co.uk, benh@...zon.com,
        ronenk@...zon.com, talel@...zon.com, jonnyc@...zon.com,
        hanochu@...zon.com, farbere@...zon.com, itamark@...zon.com,
        lareine@...zon.com
Subject: Re: [PATCH 1/1] i2c: designware: use u64 for clock freq to avoid u32
 multiplication overflow

On Wed, Dec 14, 2022 at 10:34:18AM +0000, Hanna Hawa wrote:
> From: Lareine Khawaly <lareine@...zon.com>
> 
> In functions i2c_dw_scl_lcnt() and i2c_dw_scl_hcnt() may have overflow
> by depending on the values of the given parameters including the ic_clk.
> For example in our usecase where ic_clk >= 1000000, multiplication of

It's hard to count 0:s, can you use plain words instead (like million, billion)?

> ic_clk * 4700 will result in 32 bit overflow.

> This commit change the ic_clk to be u64 parameter to avoid the overflow.

Read Submitting Patches about imperative mood in the commit messages.

...

Smells like you are missing the Fixes tag.

-- 
With Best Regards,
Andy Shevchenko


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