linux-kernel - Re: [PATCH 6/7] arm64: dts: qcom: sm8150: Add GPU speedbin support

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Message-ID: <20221215223730.4bijpy3qyplruksi@SoMainline.org>
Date:   Thu, 15 Dec 2022 23:37:30 +0100
From:   Marijn Suijten <marijn.suijten@...ainline.org>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, andersson@...nel.org,
        agross@...nel.org, krzysztof.kozlowski@...aro.org,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 6/7] arm64: dts: qcom: sm8150: Add GPU speedbin support

On 2022-12-13 01:24:22, Konrad Dybcio wrote:
> SM8150 has (at least) two GPU speed bins. With the support added on the
> driver side, wire up bin detection in the DTS to restrict lower-quality
> SKUs from running at frequencies they were not validated at.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8150.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index e160acb47cd9..3f940cc3f32b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -936,6 +936,17 @@ ethernet: ethernet@...00 {
>  			status = "disabled";
>  		};
>  
> +		qfprom: efuse@...000 {
> +			compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
> +			reg = <0 0x00784000 0 0x8ff>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			gpu_speed_bin: gpu_speed_bin@133 {
> +				reg = <0x133 0x1>;
> +				bits = <5 3>;
> +			};
> +		};
>  
>  		qupv3_id_0: geniqup@...000 {
>  			compatible = "qcom,geni-se-qup";
> @@ -2137,6 +2148,9 @@ gpu: gpu@...0000 {
>  
>  			qcom,gmu = <&gmu>;
>  
> +			nvmem-cells = <&gpu_speed_bin>;
> +			nvmem-cell-names = "speed_bin";
> +
>  			status = "disabled";
>  
>  			zap-shader {
> @@ -2150,31 +2164,37 @@ gpu_opp_table: opp-table {

Just like sm8250, you can probably delete the:

    /* note: downstream checks gpu binning for 675 Mhz */

comment right above this node.

- Marijn

>  				opp-675000000 {
>  					opp-hz = /bits/ 64 <675000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					opp-supported-hw = <0x2>;
>  				};
>  
>  				opp-585000000 {
>  					opp-hz = /bits/ 64 <585000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					opp-supported-hw = <0x3>;
>  				};
>  
>  				opp-499200000 {
>  					opp-hz = /bits/ 64 <499200000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> +					opp-supported-hw = <0x3>;
>  				};
>  
>  				opp-427000000 {
>  					opp-hz = /bits/ 64 <427000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					opp-supported-hw = <0x3>;
>  				};
>  
>  				opp-345000000 {
>  					opp-hz = /bits/ 64 <345000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					opp-supported-hw = <0x3>;
>  				};
>  
>  				opp-257000000 {
>  					opp-hz = /bits/ 64 <257000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					opp-supported-hw = <0x3>;
>  				};
>  			};
>  		};
> -- 
> 2.39.0
>