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Message-Id: <20221215065510.1621979-7-irogers@google.com>
Date: Wed, 14 Dec 2022 22:54:53 -0800
From: Ian Rogers <irogers@...gle.com>
To: Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
Adrian Hunter <adrian.hunter@...el.com>,
Kan Liang <kan.liang@...ux.intel.com>,
Xing Zhengjun <zhengjun.xing@...ux.intel.com>,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: John Garry <john.g.garry@...cle.com>,
Stephane Eranian <eranian@...gle.com>,
Perry Taylor <perry.taylor@...el.com>,
Caleb Biggers <caleb.biggers@...el.com>,
Ian Rogers <irogers@...gle.com>
Subject: [PATCH v1 15/32] perf vendor events intel: Refresh icelakex metrics
and events
Update the icelakex metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated to 1.17,
in particular uncore, with fixes to uncore events and improved
descriptions. The formatting changes increase consistency across the
json files.
Signed-off-by: Ian Rogers <irogers@...gle.com>
---
.../pmu-events/arch/x86/icelakex/cache.json | 316 +-
.../arch/x86/icelakex/floating-point.json | 28 -
.../arch/x86/icelakex/frontend.json | 140 -
.../arch/x86/icelakex/icx-metrics.json | 2192 +-
.../pmu-events/arch/x86/icelakex/memory.json | 139 +-
.../pmu-events/arch/x86/icelakex/other.json | 117 -
.../arch/x86/icelakex/pipeline.json | 344 +-
.../arch/x86/icelakex/uncore-memory.json | 1878 +-
.../arch/x86/icelakex/uncore-other.json | 45144 +++++++---------
.../arch/x86/icelakex/uncore-power.json | 115 +-
.../arch/x86/icelakex/virtual-memory.json | 88 -
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
12 files changed, 22074 insertions(+), 28429 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
index e4035b3e55ca..d6463c8d9462 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
@@ -1,1172 +1,868 @@
[
{
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of L1D misses that are outstanding",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "L2 cache lines filling L2",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1f"
},
{
"BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.NON_SILENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.SILENT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "L2 code requests",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of L2 code requests.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe4"
},
{
"BriefDescription": "Demand Data Read requests",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe1"
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts demand requests that miss L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x27"
},
{
"BriefDescription": "RFO requests to L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xe2"
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc4"
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x24"
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc1"
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x21"
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc2"
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x22"
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0xc8"
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x28"
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x41"
},
{
"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4f"
},
{
"BriefDescription": "Retired load instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
"SampleAfterValue": "1000003",
"UMask": "0x81"
},
{
"BriefDescription": "Retired store instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired store instructions.",
"SampleAfterValue": "1000003",
"UMask": "0x82"
},
{
"BriefDescription": "All retired memory instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ANY",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired memory instructions - loads and stores.",
"SampleAfterValue": "1000003",
"UMask": "0x83"
},
{
"BriefDescription": "Retired load instructions with locked access.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with locked access.",
"SampleAfterValue": "100007",
"UMask": "0x21"
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x41"
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x11"
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
"UMask": "0x12"
},
{
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
"SampleAfterValue": "20011",
"UMask": "0x4"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
+ "Deprecated": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
+ "Deprecated": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "20011",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions whose data sources was remote HITM",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Retired load instructions whose data sources was remote HITM.",
"SampleAfterValue": "100007",
"UMask": "0x4"
},
{
- "BriefDescription": "Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
"Data_LA": "1",
"EventCode": "0xd3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
+ "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
"SampleAfterValue": "100007",
"UMask": "0x10"
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).",
"SampleAfterValue": "100007",
"UMask": "0x4"
},
{
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
"SampleAfterValue": "100021",
"UMask": "0x10"
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
"SampleAfterValue": "100021",
"UMask": "0x4"
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
"SampleAfterValue": "50021",
"UMask": "0x20"
},
{
- "BriefDescription": "Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
"Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
"PEBS": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
+ "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80082380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PREFETCHES.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C27F0",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1830000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Demand and prefetch data reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts memory transactions sent to the uncore.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Counts cacheable and non-cacheable code reads to the core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts both cacheable and non-cacheable code reads to the core.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles where at least 1 outstanding data read request is pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles with outstanding code read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding code read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles the queue waiting for offcore responses is full.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SQ_FULL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
index 1925388969bb..655342dadac6 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
@@ -1,100 +1,72 @@
[
{
"BriefDescription": "Counts all microcode FP assists.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.FP",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all microcode Floating Point assists.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x2"
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
index eb27d9d9c8be..71498044f1cb 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json
@@ -1,484 +1,344 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.COUNT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x1",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x11",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x14",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x500106",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
"MSRValue": "0x508006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
"MSRValue": "0x501006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x500206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
"MSRValue": "0x510006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
"MSRValue": "0x100206",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
"MSRValue": "0x502006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
"MSRValue": "0x500406",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
"MSRValue": "0x520006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x504006",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
"MSRValue": "0x500806",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x15",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles DSB is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of switches from DSB or MITE to the MS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x30"
},
{
"BriefDescription": "Uops delivered to IDQ while MS is busy",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x30"
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
index b52afc34a169..22b2a97d0ff8 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
@@ -1,1563 +1,1529 @@
[
{
- "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
- "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS",
- "MetricGroup": "PGO;TopdownL1;tma_L1_group",
- "MetricName": "tma_frontend_bound",
- "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+ "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "Mispredictions"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
- "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLOTS",
- "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_latency",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "Memory_Bandwidth"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
- "MetricExpr": "ICACHE_16B.IFDATA_STALL / CLKS",
- "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_icache_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))",
+ "MetricGroup": "Mem;MemoryLat;Offcore",
+ "MetricName": "Memory_Latency"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
- "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS",
- "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_itlb_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
+ "MetricGroup": "Mem;MemoryTLB;Offcore",
+ "MetricName": "Memory_Data_TLBs"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
- "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_branch_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
+ "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
+ "MetricGroup": "Ret",
+ "MetricName": "Branching_Overhead"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_mispredicts_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+ "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+ "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
+ "MetricName": "Big_Code"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
- "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_clears_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+ "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
+ "MetricGroup": "Fed;FetchBW;Frontend",
+ "MetricName": "Instruction_Fetch_BW"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
- "MetricExpr": "10 * BACLEARS.ANY / CLKS",
- "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_unknown_branches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+ "MetricExpr": "INST_RETIRED.ANY / CLKS",
+ "MetricGroup": "Ret;Summary",
+ "MetricName": "IPC"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
- "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_dsb_switches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uops Per Instruction",
+ "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "UPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
- "MetricExpr": "ILD_STALL.LCP / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_lcp",
- "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW",
+ "MetricName": "UpTB"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
- "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS",
- "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_ms_switches",
- "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+ "MetricExpr": "1 / IPC",
+ "MetricGroup": "Mem;Pipeline",
+ "MetricName": "CPI"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
- "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
- "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_bandwidth",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "Pipeline",
+ "MetricName": "CLKS"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
- "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_mite",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+ "MetricExpr": "TOPDOWN.SLOTS",
+ "MetricGroup": "tma_L1_group",
+ "MetricName": "SLOTS"
},
{
- "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
- "MetricExpr": "(cpu@...T_DECODED.DECODERS\\,cmask\\=1@ - cpu@...T_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
- "MetricName": "tma_decoder0_alone",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
+ "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
+ "MetricGroup": "SMT;tma_L1_group",
+ "MetricName": "Slots_Utilization"
},
{
- "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline",
- "MetricExpr": "(cpu@....MITE_UOPS\\,cmask\\=4@ - cpu@....MITE_UOPS\\,cmask\\=5@) / CLKS",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
- "MetricName": "tma_mite_4wide",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of Executed- by Issued-Uops",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+ "MetricGroup": "Cor;Pipeline",
+ "MetricName": "Execute_per_Issue",
+ "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
- "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2",
- "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_dsb",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+ "MetricGroup": "Ret;SMT;tma_L1_group",
+ "MetricName": "CoreIPC"
},
{
- "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_bad_speculation",
- "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Floating Point Operations Per Cycle",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricGroup": "Flops;Ret",
+ "MetricName": "FLOPc"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_branch_mispredicts",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "FP_Arith_Utilization",
+ "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
- "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
- "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_machine_clears",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+ "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+ "MetricName": "ILP"
},
{
- "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + (5 * cpu@..._MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@) / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_backend_bound",
- "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+ "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "Core_Bound_Likely"
},
{
- "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
- "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_memory_bound",
- "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+ "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "SMT",
+ "MetricName": "CORE_CLKS"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
- "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l1_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+ "MetricGroup": "InsType",
+ "MetricName": "IpLoad"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
- "MetricExpr": "min(7 * cpu@...B_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_dtlb_load",
- "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+ "MetricGroup": "InsType",
+ "MetricName": "IpStore"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Fed;InsType",
+ "MetricName": "IpBranch"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "IpCall"
},
{
- "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
- "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_store_fwd_blk",
- "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+ "MetricName": "IpTB"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
- "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_lock_latency",
- "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch instructions per taken branch. ",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "BpTkBranch"
},
{
- "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
- "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_split_loads",
- "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpFLOP"
},
{
- "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
- "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_4k_aliasing",
- "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpArith",
+ "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
},
{
- "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
- "MetricExpr": "L1D_PEND_MISS.FB_FULL / CLKS",
- "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_fb_full",
- "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_SP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + L1D_PEND_MISS.FB_FULL_PERIODS)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l2_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_DP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l3_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX128",
+ "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "((44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (43.5 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_contested_accesses",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX256",
+ "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "(43.5 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_data_sharing",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX512",
+ "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "(19 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_l3_hit_latency",
- "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / cpu@...PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+ "MetricGroup": "Prefetches",
+ "MetricName": "IpSWPF"
},
{
- "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "L1D_PEND_MISS.L2_STALL / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_sq_full",
- "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+ "MetricExpr": "INST_RETIRED.ANY",
+ "MetricGroup": "Summary;tma_L1_group",
+ "MetricName": "Instructions"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound) - tma_pmm_bound)",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_dram_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
- "ScaleUnit": "100%"
- },
- {
- "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@...CORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_bandwidth",
- "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+ "MetricExpr": "tma_retiring * SLOTS / cpu@...S_RETIRED.SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "Retire"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_latency",
- "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@...S_EXECUTED.THREAD\\,cmask\\=1@",
+ "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+ "MetricName": "Execute"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
- "MetricExpr": "(43.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_local_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+ "MetricExpr": "UOPS_ISSUED.ANY / cpu@...S_ISSUED.ANY\\,cmask\\=1@",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "Fetch_UpC"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
- "MetricExpr": "(108 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+ "MetricGroup": "DSB;Fed;FetchBW",
+ "MetricName": "DSB_Coverage"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
- "MetricExpr": "((97 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (97 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_cache",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@...2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
+ "MetricGroup": "DSBmiss",
+ "MetricName": "DSB_Switch_Cost"
},
{
- "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
- "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) / ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)) if (1000000 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS) else 0)",
- "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_pmm_bound",
- "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
+ "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "DSB_Misses"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
- "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_store_bound",
- "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "IpDSB_Miss_Ret"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_store_latency",
- "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "IpMispredict"
},
{
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "(48 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "Branch_Misprediction_Cost"
},
{
- "BriefDescription": "This metric represents rate of split store accesses",
- "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
- "MetricGroup": "TopdownL4;tma_store_bound_group",
- "MetricName": "tma_split_stores",
- "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are non-taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_NT"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
- "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_streaming_stores",
- "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_TK"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
- "MetricExpr": "(7 * cpu@...B_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_dtlb_store",
- "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are CALL or RET",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "CallRet"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "Jump"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
+ "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "Other_Branches"
},
{
- "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
- "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
- "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_core_bound",
- "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
+ "MetricGroup": "Mem;MemoryBound;MemoryLat",
+ "MetricName": "Load_Miss_Real_Latency"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
- "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS",
- "MetricGroup": "TopdownL3;tma_core_bound_group",
- "MetricName": "tma_divider",
- "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
- "ScaleUnit": "100%"
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+ "MetricGroup": "Mem;MemoryBW;MemoryBound",
+ "MetricName": "MLP"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "(cpu@..._ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
- "MetricName": "tma_ports_utilization",
- "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "cpu@..._ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_0",
- "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
- "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_serializing_operation",
- "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Backend;CacheMisses;Mem",
+ "MetricName": "L2MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions",
- "MetricExpr": "37 * MISC_RETIRED.PAUSE_INST / CLKS",
- "MetricGroup": "TopdownL6;tma_serializing_operation_group",
- "MetricName": "tma_slow_pause",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
+ "MetricGroup": "CacheMisses;Mem;Offcore",
+ "MetricName": "L2MPKI_All"
},
{
- "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
- "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_mixing_vectors",
- "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2MPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_1",
- "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_2",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL",
- "ScaleUnit": "100%"
+ "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L3MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_3m",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "FB_HPKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_alu_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+ "MetricConstraint": "NO_NMI_WATCHDOG",
+ "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * CORE_CLKS)",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "Page_Walks_Utilization"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED.PORT_0",
- "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CORE_CLKS",
- "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_0",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED.PORT_1",
- "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_1",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
- "MetricExpr": "UOPS_DISPATCHED.PORT_5 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_5",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED.PORT_6",
- "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_6",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
- "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_load_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+ "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_Silent_PKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8",
- "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_store_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+ "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_NonSilent_PKI"
},
{
- "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_retiring",
- "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "L1D_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
- "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_light_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "L2_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
- "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
- "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_fp_arith",
- "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
- "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
- "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_x87_use",
- "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Access_BW",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW_1T"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_scalar",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average CPU Utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricGroup": "HPC;Summary",
+ "MetricName": "CPU_Utilization"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_vector",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+ "MetricGroup": "Power;Summary",
+ "MetricName": "Average_Frequency"
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_128b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Giga Floating Point Operations Per Second",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "GFLOPs",
+ "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_256b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+ "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricGroup": "Power",
+ "MetricName": "Turbo_Utilization"
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_512b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
+ "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License0_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
- "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_memory_operations",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
+ "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License1_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.",
- "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * SLOTS)",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_branch_instructions",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
+ "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License2_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions."
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
- "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * SLOTS)",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_nop_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
+ "MetricGroup": "SMT",
+ "MetricName": "SMT_2T_Utilization"
},
{
- "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
- "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_other_light_ops",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_Utilization"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
- "MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@...S_DECODED.DEC0\\,cmask\\=1@) / IDQ.MITE_UOPS",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_heavy_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_CPI"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
- "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
- "MetricGroup": "TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_few_uops_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "DRAM_BW_Use"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "((tma_retiring * SLOTS) / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
- "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_microcode_sequencer",
- "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
},
{
- "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
- "MetricExpr": "100 * ASSISTS.ANY / SLOTS",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_assists",
- "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@...esh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
- "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_cisc",
- "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@...nt\\=0x0@",
+ "MetricGroup": "Mem;MemoryLat;Server;SoC",
+ "MetricName": "MEM_PMM_Read_Latency"
},
{
- "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
- "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "Mispredictions"
+ "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@...nt\\=0x0@",
+ "MetricGroup": "Mem;MemoryLat;Server;SoC",
+ "MetricName": "MEM_DRAM_Read_Latency"
},
{
- "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "Memory_Bandwidth"
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
+ "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Server;SoC",
+ "MetricName": "PMM_Read_BW"
},
{
- "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)))",
- "MetricGroup": "Mem;MemoryLat;Offcore",
- "MetricName": "Memory_Latency"
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Server;SoC",
+ "MetricName": "PMM_Write_BW"
},
{
- "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
- "MetricGroup": "Mem;MemoryTLB;Offcore",
- "MetricName": "Memory_Data_TLBs"
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;Mem;Server;SoC",
+ "MetricName": "IO_Write_BW"
},
{
- "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
- "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
- "MetricGroup": "Ret",
- "MetricName": "Branching_Overhead"
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;Mem;Server;SoC",
+ "MetricName": "IO_Read_BW"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
- "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
- "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
- "MetricName": "Big_Code"
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "cha_0@...nt\\=0x0@",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
- "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
- "MetricGroup": "Fed;FetchBW;Frontend",
- "MetricName": "Instruction_Fetch_BW"
+ "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+ "MetricGroup": "Branches;OS",
+ "MetricName": "IpFarBranch"
},
{
- "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
- "MetricExpr": "INST_RETIRED.ANY / CLKS",
- "MetricGroup": "Ret;Summary",
- "MetricName": "IPC"
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
},
{
- "BriefDescription": "Uops Per Instruction",
- "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;Ret;Retire",
- "MetricName": "UPI"
+ "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricName": "cpu_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW",
- "MetricName": "UpTB"
+ "BriefDescription": "CPU operating frequency (in GHz)",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+ "MetricName": "cpu_operating_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
- "MetricExpr": "1 / IPC",
- "MetricGroup": "Mem;Pipeline",
- "MetricName": "CPI"
+ "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+ "MetricName": "cpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "Pipeline",
- "MetricName": "CLKS"
+ "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+ "MetricName": "loads_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
- "MetricExpr": "TOPDOWN.SLOTS",
- "MetricGroup": "tma_L1_group",
- "MetricName": "SLOTS"
+ "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+ "MetricName": "stores_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
- "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
- "MetricGroup": "SMT;tma_L1_group",
- "MetricName": "Slots_Utilization"
+ "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+ "MetricName": "l1d_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "The ratio of Executed- by Issued-Uops",
- "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
- "MetricGroup": "Cor;Pipeline",
- "MetricName": "Execute_per_Issue",
- "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+ "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+ "MetricName": "l1d_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
- "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
- "MetricGroup": "Ret;SMT;tma_L1_group",
- "MetricName": "CoreIPC"
+ "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+ "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
- "MetricGroup": "Flops;Ret",
- "MetricName": "FLOPc"
+ "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "FP_Arith_Utilization",
- "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+ "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+ "MetricName": "l2_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
- "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
- "MetricName": "ILP"
+ "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
- "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
- "MetricGroup": "Cor;SMT",
- "MetricName": "Core_Bound_Likely"
+ "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_code_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
- "MetricGroup": "SMT",
- "MetricName": "CORE_CLKS"
+ "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY",
+ "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
- "MetricGroup": "InsType",
- "MetricName": "IpLoad"
+ "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY",
+ "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
- "MetricGroup": "InsType",
- "MetricName": "IpStore"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Branches;Fed;InsType",
- "MetricName": "IpBranch"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "IpCall"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
- "MetricName": "IpTB"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Branch instructions per taken branch. ",
- "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "BpTkBranch"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time",
+ "MetricName": "llc_demand_data_read_miss_to_dram_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpFLOP"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "itlb_2nd_level_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpArith",
- "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "itlb_2nd_level_large_page_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_SP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_DP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX128",
- "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2nd_level_store_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX256",
- "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+ "MetricName": "numa_reads_addressed_to_local_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX512",
- "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)",
+ "MetricName": "numa_reads_addressed_to_remote_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / cpu@...PREFETCH_ACCESS.T0\\,umask\\=0xF@",
- "MetricGroup": "Prefetches",
- "MetricName": "IpSWPF"
+ "BriefDescription": "Uncore operating frequency in GHz",
+ "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
+ "MetricName": "uncore_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
- "MetricExpr": "INST_RETIRED.ANY",
- "MetricGroup": "Summary;tma_L1_group",
- "MetricName": "Instructions"
+ "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+ "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+ "MetricName": "upi_data_transmit_bw",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "(tma_retiring * SLOTS) / cpu@...S_RETIRED.SLOTS\\,cmask\\=1@",
- "MetricGroup": "Pipeline;Ret",
- "MetricName": "Retire"
+ "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "",
- "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@...S_EXECUTED.THREAD\\,cmask\\=1@",
- "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
- "MetricName": "Execute"
+ "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Average number of Uops issued by front-end when it issued something",
- "MetricExpr": "UOPS_ISSUED.ANY / cpu@...S_ISSUED.ANY\\,cmask\\=1@",
- "MetricGroup": "Fed;FetchBW",
- "MetricName": "Fetch_UpC"
+ "BriefDescription": "DDR memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
- "MetricGroup": "DSB;Fed;FetchBW",
- "MetricName": "DSB_Coverage"
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@...2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
- "MetricGroup": "DSBmiss",
- "MetricName": "DSB_Switch_Cost"
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
- "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "DSB_Misses"
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "IpDSB_Miss_Ret"
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR + UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_writes",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "IpMispredict"
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_reads",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BrMispredicts",
- "MetricName": "Branch_Misprediction_Cost"
+ "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_decoded_icache",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are non-taken conditionals",
- "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_NT"
+ "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are taken conditionals",
- "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_TK"
+ "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are CALL or RET",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "CallRet"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "Jump"
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
- "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
- "MetricGroup": "Bad;Branches",
- "MetricName": "Other_Branches"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
- "MetricGroup": "Mem;MemoryBound;MemoryLat",
- "MetricName": "Load_Miss_Real_Latency"
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
- "MetricGroup": "Mem;MemoryBW;MemoryBound",
- "MetricName": "MLP"
+ "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+ "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots",
+ "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_frontend_bound",
+ "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+ "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots",
+ "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_latency",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI_Load"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+ "MetricExpr": "ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_icache_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "Backend;CacheMisses;Mem",
- "MetricName": "L2MPKI"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+ "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_itlb_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * ((OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions",
- "MetricGroup": "CacheMisses;Mem;Offcore",
- "MetricName": "L2MPKI_All"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+ "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_branch_resteers",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2MPKI_Load"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_mispredicts_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_Load"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+ "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_clears_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L3MPKI"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+ "MetricExpr": "10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_unknown_branches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "FB_HPKI"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_dsb_switches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
- "MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * CORE_CLKS)",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "Page_Walks_Utilization"
+ "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+ "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_lcp",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+ "MetricExpr": "3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_ms_switches",
+ "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+ "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
+ "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_bandwidth",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+ "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_mite",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+ "MetricExpr": "(cpu@...T_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@...T_DECODED.DECODERS\\,cmask\\=0x2@) / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+ "MetricName": "tma_decoder0_alone",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW"
+ "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline",
+ "MetricExpr": "(cpu@....MITE_UOPS\\,cmask\\=0x4@ - cpu@....MITE_UOPS\\,cmask\\=0x5@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+ "MetricName": "tma_mite_4wide",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
- "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_Silent_PKI"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+ "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2",
+ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_dsb",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
- "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_NonSilent_PKI"
+ "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+ "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_bad_speculation",
+ "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "L1D_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_branch_mispredicts",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "L2_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+ "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_machine_clears",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW_1T"
+ "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+ "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@..._MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ / slots",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_backend_bound",
+ "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Access_BW",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW_1T"
+ "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
+ "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_memory_bound",
+ "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
- "MetricGroup": "HPC;Summary",
- "MetricName": "CPU_Utilization"
+ "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+ "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l1_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
- "MetricGroup": "Power;Summary",
- "MetricName": "Average_Frequency"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+ "MetricExpr": "min(7 * cpu@...B_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_dtlb_load",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "GFLOPs",
- "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average Frequency Utilization relative nominal frequency",
- "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
- "MetricGroup": "Power",
- "MetricName": "Turbo_Utilization"
+ "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
- "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License0_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
+ "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+ "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_store_fwd_blk",
+ "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
- "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License1_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
+ "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+ "MetricExpr": "min((16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_lock_latency",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
- "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License2_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions."
+ "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+ "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_split_loads",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
- "MetricGroup": "SMT",
- "MetricName": "SMT_2T_Utilization"
+ "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+ "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_4k_aliasing",
+ "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "OS",
- "MetricName": "Kernel_Utilization"
+ "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+ "MetricExpr": "L1D_PEND_MISS.FB_FULL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_fb_full",
+ "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
- "MetricGroup": "OS",
- "MetricName": "Kernel_CPI"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l2_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@..._count_read@ + uncore_imc@..._count_write@) / 1000000000) / duration_time",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC",
- "MetricName": "DRAM_BW_Use"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l3_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
- "MetricGroup": "Mem;MemoryLat;SoC",
- "MetricName": "MEM_Read_Latency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+ "MetricExpr": "min(((48 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_contested_accesses",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@...nt\\=0x36\\,umask\\=0xC817FE01\\,thresh\\=1@",
- "MetricGroup": "Mem;MemoryBW;SoC",
- "MetricName": "MEM_Parallel_Reads"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+ "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_data_sharing",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
- "MetricExpr": "(1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@...nt\\=0x0@)",
- "MetricGroup": "Mem;MemoryLat;Server;SoC",
- "MetricName": "MEM_PMM_Read_Latency"
+ "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+ "MetricExpr": "min((23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_l3_hit_latency",
+ "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
- "MetricExpr": " 1000000000 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@...nt\\=0x0@",
- "MetricGroup": "Mem;MemoryLat;Server;SoC",
- "MetricName": "MEM_DRAM_Read_Latency"
+ "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+ "MetricExpr": "L1D_PEND_MISS.L2_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_sq_full",
+ "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
- "MetricExpr": "((64 * imc@...nt\\=0xe3@ / 1000000000) / duration_time)",
- "MetricGroup": "Mem;MemoryBW;Server;SoC",
- "MetricName": "PMM_Read_BW"
+ "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+ "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound - min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1), 1)",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_dram_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
- "MetricExpr": "((64 * imc@...nt\\=0xe7@ / 1000000000) / duration_time)",
- "MetricGroup": "Mem;MemoryBW;Server;SoC",
- "MetricName": "PMM_Write_BW"
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@...CORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_bandwidth",
+ "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
- "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000000 / duration_time",
- "MetricGroup": "IoBW;Mem;Server;SoC",
- "MetricName": "IO_Write_BW"
+ "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_latency",
+ "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
- "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1000000000 / duration_time",
- "MetricGroup": "IoBW;Mem;Server;SoC",
- "MetricName": "IO_Read_BW"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+ "MetricExpr": "min((66.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_local_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Socket actual clocks when any core is active on that socket",
- "MetricExpr": "cha_0@...nt\\=0x0@",
- "MetricGroup": "SoC",
- "MetricName": "Socket_CLKS"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+ "MetricExpr": "min((131 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
- "MetricGroup": "Branches;OS",
- "MetricName": "IpFarBranch"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+ "MetricExpr": "min(((120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_cache",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C1 residency percent per core",
- "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C1_Core_Residency"
+ "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
+ "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)",
+ "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_pmm_bound",
+ "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+ "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_store_bound",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_store_latency",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+ "MetricExpr": "min(48 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_false_sharing",
+ "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "BriefDescription": "This metric represents rate of split store accesses",
+ "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_split_stores",
+ "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "CPU operating frequency (in GHz)",
- "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "cpu_operating_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores",
+ "MetricExpr": "min(9 * OCR.STREAMING_WR.ANY_RESPONSE / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_streaming_stores",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "loads_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+ "MetricExpr": "min((7 * cpu@...B_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CPU_CLK_UNHALTED.DISTRIBUTED, 1)",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_dtlb_store",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "stores_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+ "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
+ "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_core_bound",
+ "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+ "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_divider",
+ "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+ "MetricExpr": "((cpu@..._ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) + 0 * slots",
+ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_ports_utilization",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "cpu@..._ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CPU_CLK_UNHALTED.THREAD + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_0",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+ "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_serializing_operation",
+ "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.",
+ "MetricExpr": "37 * MISC_RETIRED.PAUSE_INST / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group",
+ "MetricName": "tma_slow_pause",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_code_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_mixing_vectors",
+ "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_1",
+ "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_2",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+ "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_3m",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_latency_for_local_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+ "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_alu_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_0",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_to_pmem_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_1",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds",
- "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_demand_data_read_miss_to_dram_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_5 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_5",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_2nd_level_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CPU_CLK_UNHALTED.DISTRIBUTED",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_6",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_2nd_level_large_page_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+ "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_load_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2nd_level_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+ "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_store_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_retiring",
+ "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2nd_level_store_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+ "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - tma_heavy_operations)",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_light_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_local_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector",
+ "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fp_arith",
+ "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE ) / ( UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_remote_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + 0 * slots",
+ "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_x87_use",
+ "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore operating frequency in GHz",
- "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "uncore_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_scalar",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
- "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "upi_data_transmit_bw",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_vector",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_128b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_256b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_512b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+ "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_memory_operations",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.",
+ "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_branch_instructions",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+ "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_nop_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
- "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR + UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_writes",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+ "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_other_light_ops",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
- "MetricExpr": "(( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_reads",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+ "MetricExpr": "tma_microcode_sequencer + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * (UOPS_DECODED.DEC0 - cpu@...S_DECODED.DEC0\\,cmask\\=0x1@) / IDQ.MITE_UOPS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_heavy_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_decoded_icache",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+ "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_few_uops_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+ "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots / UOPS_ISSUED.ANY * IDQ.MS_UOPS / slots",
+ "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_microcode_sequencer",
+ "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_microcode_sequencer",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+ "MetricExpr": "min(100 * ASSISTS.ANY / slots, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_assists",
+ "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+ "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_cisc",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C1 residency percent per core",
+ "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C1_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_remote_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C6 residency percent per core",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_remote_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C2 residency percent per package",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "%",
- "MetricExpr": "100 * ( ( LSD.CYCLES_ACTIVE - LSD.CYCLES_OK ) / ( CPU_CLK_UNHALTED.DISTRIBUTED ) / 2 )",
- "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
- "MetricName": "tma_lsd",
- "ScaleUnit": "1%"
+ "BriefDescription": "C6 residency percent per package",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
index 48e8d1102b9d..f36ac04f8d76 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
@@ -1,549 +1,414 @@
[
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x6"
},
{
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F04400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94002380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84002380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ITOM.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PREFETCHES.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F844027F0",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC00477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F04400477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70CC00477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data read requests that miss the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
- "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Number of times an RTM execution aborted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM abort was triggered.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
"SampleAfterValue": "100003",
"UMask": "0x40"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM commit succeeded.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_READ",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json
index 919e620e7db8..63d5faf2fc43 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json
@@ -1,576 +1,459 @@
[
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x18"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Hit snoop reply with data, line invalidated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.I_FWD_FE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x20"
},
{
"BriefDescription": "HitM snoop reply with data, line invalidated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.I_FWD_M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Hit snoop reply without sending the data, line invalidated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.I_HIT_FSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Line not found snoop reply",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.MISS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Hit snoop reply with data, line kept in Shared state.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.S_FWD_FE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "HitM snoop reply with data, line kept in Shared state",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.S_FWD_M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Hit snoop reply without sending the data, line kept in Shared state.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xef",
"EventName": "CORE_SNOOP_RESPONSE.S_HIT_FSE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core.",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703C00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703C00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch (which bring data to L2) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10070",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x12380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90002380",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ITOM.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC0477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70C000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700C00477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F33000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x731800477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800477",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.WRITE_ESTIMATE.MEMORY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFBFF80822",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
index 52fba238bf1f..4cf16a1fcad4 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
@@ -1,701 +1,489 @@
[
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x9"
},
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "All branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all branch instructions retired.",
"SampleAfterValue": "400009"
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x11"
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts not taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x10"
},
{
"BriefDescription": "Taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x1"
},
{
"BriefDescription": "Far branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts far branch instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x40"
},
{
"BriefDescription": "Indirect near branch instructions retired (excluding returns)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
"SampleAfterValue": "100003",
"UMask": "0x80"
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts both direct and indirect near call instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x2"
},
{
"BriefDescription": "Return instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts return instructions retired.",
"SampleAfterValue": "100007",
"UMask": "0x8"
},
{
"BriefDescription": "Taken branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken branch instructions retired.",
"SampleAfterValue": "400009",
"UMask": "0x20"
},
{
"BriefDescription": "All mispredicted branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
"SampleAfterValue": "50021"
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts mispredicted conditional branch instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x11"
},
{
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
"SampleAfterValue": "50021",
"UMask": "0x10"
},
{
"BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x1"
},
{
"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
"SampleAfterValue": "50021",
"UMask": "0x80"
},
{
"BriefDescription": "Mispredicted indirect CALL instructions retired.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect.",
"SampleAfterValue": "50021",
"UMask": "0x2"
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
"SampleAfterValue": "50021",
"UMask": "0x20"
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x8"
},
{
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"SampleAfterValue": "25003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
- "PEBScounters": "34",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x3"
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
"SampleAfterValue": "25003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
- "PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
- "SampleAfterValue": "2000003",
- "Speculative": "1"
+ "SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0xc"
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
- "PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x5"
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "20",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x14"
},
{
"BriefDescription": "Total execution stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Number of all retired NOP instructions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.NOP",
"PEBS": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.PREC_DIST",
"PEBS": "1",
- "PEBScounters": "32",
"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x3"
},
{
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
"SampleAfterValue": "500009",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots where uops got dropped",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0d",
"EventName": "INT_MISC.UOP_DROPPING",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "False dependencies due to partial compare on address.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xa8",
"EventName": "LSD.CYCLES_OK",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.COUNT",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of machine clears (nukes) of any type.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.LBR_INSERTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.",
"SampleAfterValue": "100003",
"UMask": "0x20"
},
{
"BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xcc",
"EventName": "MISC_RETIRED.PAUSE_INST",
"PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
@@ -704,399 +492,273 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SB",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SCOREBOARD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x5e",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_END",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 3",
"EventName": "TOPDOWN.SLOTS",
- "PEBScounters": "35",
"PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.SLOTS_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
"SampleAfterValue": "10000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UOPS_DECODED.DEC0",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Uops exclusively fetched by decoder 0",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 0",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_0",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 1",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of uops executed on port 2 and 3",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_2_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of uops executed on port 4 and 9",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_4_9",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Number of uops executed on port 5",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_5",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Number of uops executed on port 6",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_6",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Number of uops executed on port 7 and 8",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_7_8",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x80"
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.THREAD",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of x87 uops executed.",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Uops that RAT issues to RS",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
"SampleAfterValue": "2000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
+ "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Retirement slots used.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the retirement slots used each cycle.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts cycles without actually retired uops.",
"SampleAfterValue": "1000003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "10",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"Invert": "1",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.",
+ "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
}
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
index 6872ae4b29d9..0d495ae53f3d 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json
@@ -1,1856 +1,1546 @@
[
{
- "BriefDescription": "2LM Tag Check : Hit in Near Memory Cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.HIT",
+ "BriefDescription": "DRAM Activate Count : All Activates",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_ACT_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "2LM Tag Check : Miss, no data in this line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
+ "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
+ "BriefDescription": "All DRAM CAS commands issued",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
+ "UMask": "0x3f",
"Unit": "iMC"
},
{
- "BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.NM_RD_HIT",
+ "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills.",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.NM_WR_HIT",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with explicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to read",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.RD",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.WR",
+ "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the total number of DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM underfill read CAS commands issued",
"EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD",
+ "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x0f",
+ "PublicDescription": "Counts the total of DRAM Read CAS commands issued due to an underfill",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "All DRAM write CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
"UMask": "0x30",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
"EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.ALL",
- "PerPkg": "1",
- "UMask": "0x3f",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+ "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.WR_PRE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS.PCH0",
+ "BriefDescription": "DRAM Clockticks",
+ "EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS.PCH1",
+ "BriefDescription": "Free running counter that increments for the Memory Controller",
+ "EventName": "UNC_M_CLOCKTICKS_FREERUN",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS.PCH0",
+ "BriefDescription": "DRAM Precharge All Commands",
+ "EventCode": "0x44",
+ "EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent.",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS.PCH1",
+ "BriefDescription": "Number of DRAM Refreshes Issued",
+ "EventCode": "0x45",
+ "EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.PGT",
+ "BriefDescription": "Number of DRAM Refreshes Issued",
+ "EventCode": "0x45",
+ "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventName": "UNC_M_CLOCKTICKS",
+ "BriefDescription": "Number of DRAM Refreshes Issued",
+ "EventCode": "0x45",
+ "EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
+ "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Half clockticks for IMC",
- "Counter": "FIXED",
- "CounterType": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_M_HCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
+ "BriefDescription": "UNC_M_PARITY_ERRORS",
+ "EventCode": "0x2c",
+ "EventName": "UNC_M_PARITY_ERRORS",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
+ "BriefDescription": "UNC_M_PCLS.RD",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_PCLS.RD",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
+ "BriefDescription": "UNC_M_PCLS.TOTAL",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_PCLS.TOTAL",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
+ "BriefDescription": "UNC_M_PCLS.WR",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_PCLS.WR",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count : All Activates",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M_ACT_COUNT.ALL",
+ "BriefDescription": "PMM Commands : All",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.ALL",
"PerPkg": "1",
- "UMask": "0x0B",
+ "PublicDescription": "PMM Commands : All : Counts all commands issued to PMM",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.ALL",
+ "BriefDescription": "PMM Commands : Misc Commands (error, flow ACKs)",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.MISC",
"PerPkg": "1",
- "UMask": "0x1C",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
+ "BriefDescription": "PMM Commands : Misc GNTs",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M_PMM_RPQ_INSERTS",
+ "BriefDescription": "PMM Commands : Reads - RPQ",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.RD",
"PerPkg": "1",
+ "PublicDescription": "PMM Commands : Reads - RPQ : Counts read requests issued to the PMM RPQ",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE7",
- "EventName": "UNC_M_PMM_WPQ_INSERTS",
+ "BriefDescription": "PMM Commands : RPQ GNTs",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
"PerPkg": "1",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "PMM Commands : Underfill reads",
"EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.ALL",
+ "EventName": "UNC_M_PMM_CMD1.UFILL_RD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PMM Commands : Underfill reads : Counts underfill read commands, due to a partial write, issued to PMM",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Reads - RPQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "PMM Commands : Underfill GNTs",
"EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.RD",
+ "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "PMM Commands : Writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.WR",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "PMM Commands : Writes : Counts write commands issued to PMM",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Underfill reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.UFILL_RD",
+ "BriefDescription": "PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding)",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
+ "BriefDescription": "PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP)",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M_RDB_INSERTS",
+ "BriefDescription": "PMM Commands - Part 2 : Opportunistic Reads",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.OPP_RD",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Accepted",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.ACCEPTS",
+ "BriefDescription": "PMM Commands - Part 2 : ECC Errors",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
"PerPkg": "1",
- "UMask": "0x05",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Rejected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.REJECTS",
+ "BriefDescription": "PMM Commands - Part 2 : ERID detectable parity error",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
"PerPkg": "1",
- "UMask": "0x0A",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_REG",
+ "BriefDescription": "PMM Commands - Part 2",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.PMM_ERID_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM underfill read CAS commands issued",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 0",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M_ACT_COUNT.BYP",
+ "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 1",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
+ "BriefDescription": "PMM Read Queue Cycles Full",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
+ "BriefDescription": "PMM Read Queue Cycles Not Empty",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.WR_PRE",
+ "BriefDescription": "PMM Read Queue Inserts",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M_PMM_RPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "PMM Read Queue Inserts : Counts number of read requests allocated in the PMM Read Pending Queue. This includes both ISOCH and non-ISOCH requests.",
"Unit": "iMC"
},
{
- "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
+ "BriefDescription": "PMM Read Pending Queue Occupancy",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
+ "BriefDescription": "PMM Write Queue Cycles Full",
+ "EventCode": "0xE6",
+ "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x08",
"Unit": "iMC"
},
{
- "BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
+ "BriefDescription": "PMM Write Queue Cycles Not Empty",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
+ "BriefDescription": "UNC_M_PMM_WPQ_FLUSH",
+ "EventCode": "0xe8",
+ "EventName": "UNC_M_PMM_WPQ_FLUSH",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
+ "BriefDescription": "UNC_M_PMM_WPQ_FLUSH_CYC",
+ "EventCode": "0xe9",
+ "EventName": "UNC_M_PMM_WPQ_FLUSH_CYC",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Throttle Cycles for Rank 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
+ "BriefDescription": "PMM Write Queue Inserts",
+ "EventCode": "0xE7",
+ "EventName": "UNC_M_PMM_WPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PMM Write Queue Inserts : Counts number of write requests allocated in the PMM Write Pending Queue.",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
+ "BriefDescription": "PMM Write Pending Queue Occupancy",
+ "EventCode": "0xE4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
+ "BriefDescription": "PMM Write Pending Queue Occupancy",
+ "EventCode": "0xE4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Read Accepts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
+ "BriefDescription": "PMM Write Pending Queue Occupancy",
+ "EventCode": "0xE4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Read Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
+ "BriefDescription": "Channel PPD Cycles",
+ "EventCode": "0x85",
+ "EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : NM read completions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : NM write completions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : FM read completions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : FM write completions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
+ "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
+ "EventCode": "0x47",
+ "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Write Accepts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
+ "BriefDescription": "Throttle Cycles for Rank 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses : Write Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
+ "BriefDescription": "Throttle Cycles for Rank 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Alloc",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.ALLOC",
+ "BriefDescription": "Clock-Enabled Self-Refresh",
+ "EventCode": "0x43",
+ "EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Dealloc",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.DEALLOC",
+ "BriefDescription": "Throttle Cycles for Rank 0",
+ "EventCode": "0x46",
+ "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Reject",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.VLD",
+ "BriefDescription": "Throttle Cycles for Rank 0",
+ "EventCode": "0x46",
+ "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
+ "BriefDescription": "DRAM Precharge commands.",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x1c",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to page miss",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests)",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.PGT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to read",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd9",
- "EventName": "UNC_M_SB_CANARY.FMTGRWR_STARVED",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to write",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.RDS",
+ "BriefDescription": "Read Data Buffer Full",
+ "EventCode": "0x19",
+ "EventName": "UNC_M_RDB_FULL",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.WRS",
+ "BriefDescription": "Read Data Buffer Inserts",
+ "EventCode": "0x17",
+ "EventName": "UNC_M_RDB_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Block region reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
+ "BriefDescription": "Read Data Buffer Not Empty",
+ "EventCode": "0x18",
+ "EventName": "UNC_M_RDB_NOT_EMPTY",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Block region writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
+ "BriefDescription": "Read Data Buffer Occupancy",
+ "EventCode": "0x1A",
+ "EventName": "UNC_M_RDB_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.RDS",
+ "BriefDescription": "Read Pending Queue Full Cycles",
+ "EventCode": "0x12",
+ "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Block region reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
+ "BriefDescription": "Read Pending Queue Full Cycles",
+ "EventCode": "0x15",
+ "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Block region writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
+ "BriefDescription": "Read Pending Queue Not Empty",
+ "EventCode": "0x11",
+ "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
+ "BriefDescription": "Read Pending Queue Not Empty",
+ "EventCode": "0x11",
+ "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS.PCH0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS.PCH1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.CANARY",
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x80",
+ "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NMRD",
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x81",
+ "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FMRD",
+ "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Accepted",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.ACCEPTS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NMWR",
+ "EventCode": "0xd2",
+ "EventName": "UNC_M_SB_ACCESSES.FMRD_CMPS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FMWR",
+ "EventCode": "0xd2",
+ "EventName": "UNC_M_SB_ACCESSES.FMWR_CMPS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FMTGR",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.NMRD",
+ "BriefDescription": "Scoreboard Accesses : Write Accepts",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FMRD",
+ "BriefDescription": "Scoreboard Accesses : Write Rejects",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.NMWR",
+ "EventCode": "0xd2",
+ "EventName": "UNC_M_SB_ACCESSES.NMRD_CMPS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FMWR",
+ "EventCode": "0xd2",
+ "EventName": "UNC_M_SB_ACCESSES.NMWR_CMPS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xde",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FMTGR",
+ "BriefDescription": "Scoreboard Accesses : FM read completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.NMRD",
+ "BriefDescription": "Scoreboard Accesses : FM write completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.FMRD",
+ "BriefDescription": "Scoreboard Accesses : Read Accepts",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.NMWR",
+ "BriefDescription": "Scoreboard Accesses : Read Rejects",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.FMWR",
+ "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Rejected",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.REJECTS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd8",
- "EventName": "UNC_M_SB_STRV_OCC.FMTGR",
+ "BriefDescription": "Scoreboard Accesses : NM read completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.NEW",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.NEW",
+ "BriefDescription": "Scoreboard Accesses : NM write completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.RD_HIT",
+ "BriefDescription": ": Alloc",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.ALLOC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.RD_MISS",
+ "BriefDescription": ": Dealloc",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.DEALLOC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_RD_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.OCC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.OCC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.FMTGRWR_STARVED",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.FM_WR_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
+ "BriefDescription": ": Near Mem Write Starved",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
+ "BriefDescription": ": Far Mem Write Starved",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
+ "BriefDescription": ": Far Mem Read Starved",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_RD_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_CANARY.NM_WR_STARVED",
+ "Deprecated": "1",
+ "EventCode": "0xd9",
+ "EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PCLS.RD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M_PCLS.RD",
+ "BriefDescription": ": Valid",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PCLS.WR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M_PCLS.WR",
+ "BriefDescription": ": Near Mem Read Starved",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PCLS.TOTAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M_PCLS.TOTAL",
+ "BriefDescription": ": Reject",
+ "EventCode": "0xD9",
+ "EventName": "UNC_M_SB_CANARY.VLD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Inserts : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDA",
- "EventName": "UNC_M_SB_PREF_INSERTS.ALL",
+ "BriefDescription": "Scoreboard Cycles Full",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M_SB_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Occupancy : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDB",
- "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL",
+ "BriefDescription": "Scoreboard Cycles Not-Empty",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M_SB_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP",
+ "BriefDescription": "Scoreboard Inserts : Block region reads",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M_DRAM_PRE_ALL",
+ "BriefDescription": "Scoreboard Inserts : Block region writes",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
"PerPkg": "1",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PARITY_ERRORS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2c",
- "EventName": "UNC_M_PARITY_ERRORS",
+ "BriefDescription": "Scoreboard Inserts : Persistent Mem reads",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Channel PPD Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M_POWER_CHANNEL_PPD",
+ "BriefDescription": "Scoreboard Inserts : Persistent Mem writes",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
"PerPkg": "1",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Clock-Enabled Self-Refresh",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M_POWER_SELF_REFRESH",
+ "BriefDescription": "Scoreboard Inserts : Reads",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.RDS",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M_RDB_FULL",
+ "BriefDescription": "Scoreboard Inserts : Writes",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.WRS",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M_RDB_NOT_EMPTY",
+ "BriefDescription": "Scoreboard Occupancy : Block region reads",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
"PerPkg": "1",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Data Buffer Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1A",
- "EventName": "UNC_M_RDB_OCCUPANCY",
+ "BriefDescription": "Scoreboard Occupancy : Block region writes",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
"PerPkg": "1",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
+ "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
+ "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
"PerPkg": "1",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M_SB_CYCLES_FULL",
+ "BriefDescription": "Scoreboard Occupancy : Reads",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.RDS",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Cycles Not-Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M_SB_CYCLES_NE",
+ "BriefDescription": "Scoreboard Prefetch Inserts : All",
+ "EventCode": "0xDA",
+ "EventName": "UNC_M_SB_PREF_INSERTS.ALL",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
+ "BriefDescription": "Scoreboard Prefetch Inserts : DDR4",
+ "EventCode": "0xDA",
+ "EventName": "UNC_M_SB_PREF_INSERTS.DDR",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
+ "BriefDescription": "Scoreboard Prefetch Inserts : Persistent Mem",
+ "EventCode": "0xDA",
+ "EventName": "UNC_M_SB_PREF_INSERTS.PMM",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
+ "BriefDescription": "Scoreboard Prefetch Occupancy : All",
+ "EventCode": "0xDB",
+ "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to page miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4",
+ "EventCode": "0xDB",
+ "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR",
"PerPkg": "1",
- "UMask": "0x0c",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_PREF_OCCUPANCY.PMM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"Deprecated": "1",
"EventCode": "0xdb",
"EventName": "UNC_M_SB_PREF_OCCUPANCY.PMEM",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd2",
- "EventName": "UNC_M_SB_ACCESSES.NMRD_CMPS",
+ "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem",
+ "EventCode": "0xdb",
+ "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0xd2",
- "EventName": "UNC_M_SB_ACCESSES.NMWR_CMPS",
+ "BriefDescription": "Number of Scoreboard Requests Rejected",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.CANARY",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : RPQ GNTs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
+ "BriefDescription": "Number of Scoreboard Requests Rejected",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Underfill GNTs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
+ "BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Misc GNTs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
+ "BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands : Misc Commands (error, flow ACKs)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.MISC",
+ "BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Opportunistic Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.OPP_RD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FMRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Expected No data packet (ERID matched NDP encoding)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_TGR",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FMTGR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Unexpected No data packet (ERID matched a Read, but data was a NDP)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.FM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FMWR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
+ "BriefDescription": ": Far Mem Read - Set",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
+ "BriefDescription": ": Near Mem Read - Clear",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : ECC Errors",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
+ "BriefDescription": ": Far Mem Write - Set",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2 : ERID detectable parity error",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NMRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Commands - Part 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.PMM_ERID_STARVED",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NMWR",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT",
+ "BriefDescription": ": Near Mem Read - Set",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
+ "BriefDescription": ": Near Mem Write - Set",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FMRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_TGR",
+ "Deprecated": "1",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FMTGR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.FM_WR",
"Deprecated": "1",
- "EventCode": "0xd2",
- "EventName": "UNC_M_SB_ACCESSES.FMRD_CMPS",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FMWR",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": ": Far Mem Read - Set",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": ": Near Mem Read - Clear",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": ": Far Mem Write - Set",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD",
"Deprecated": "1",
- "EventCode": "0xd2",
- "EventName": "UNC_M_SB_ACCESSES.FMWR_CMPS",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.NMRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Persistent Mem reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xde",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.NMWR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts : Persistent Mem writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
+ "BriefDescription": ": Near Mem Read - Set",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
+ "BriefDescription": ": Near Mem Write - Set",
+ "EventCode": "0xDE",
+ "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.FMRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_TGR",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.FMTGR",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.FM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.FMWR",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "BriefDescription": ": Far Mem Read",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.FM_RD",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Inserts : DDR4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDA",
- "EventName": "UNC_M_SB_PREF_INSERTS.DDR",
+ "BriefDescription": ": Near Mem Read - Clear",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.FM_TGR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Inserts : Persistent Mem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDA",
- "EventName": "UNC_M_SB_PREF_INSERTS.PMM",
+ "BriefDescription": ": Far Mem Write",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.FM_WR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDB",
- "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.NMRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Queue Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_WR",
+ "Deprecated": "1",
+ "EventCode": "0xd8",
+ "EventName": "UNC_M_SB_STRV_OCC.NMWR",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Read Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
+ "BriefDescription": ": Near Mem Read",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.NM_RD",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Queue Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
+ "BriefDescription": ": Near Mem Write",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.NM_WR",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "PMM Write Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
+ "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
"PerPkg": "1",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PMM_WPQ_FLUSH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe8",
- "EventName": "UNC_M_PMM_WPQ_FLUSH",
+ "BriefDescription": "UNC_M_SB_TAGGED.NEW",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.NEW",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_PMM_WPQ_FLUSH_CYC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe9",
- "EventName": "UNC_M_PMM_WPQ_FLUSH_CYC",
+ "BriefDescription": "UNC_M_SB_TAGGED.OCC",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.OCC",
"PerPkg": "1",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xdb",
- "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM",
+ "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Free running counter that increments for the Memory Controller",
- "Counter": "4",
- "CounterType": "FREERUN",
- "EventName": "UNC_M_CLOCKTICKS_FREERUN",
+ "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
"PerPkg": "1",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": ": Valid",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED",
+ "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read Starved",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED",
+ "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.RD_HIT",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Write Starved",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED",
+ "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.RD_MISS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Read Starved",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED",
+ "BriefDescription": "2LM Tag Check : Hit in Near Memory Cache",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.HIT",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Write Starved",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED",
+ "BriefDescription": "2LM Tag Check : Miss, no data in this line",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD",
+ "BriefDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Read - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD",
+ "BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.NM_RD_HIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Write - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR",
+ "BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cache",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.NM_WR_HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Write - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR",
+ "BriefDescription": "Write Pending Queue Full Cycles",
+ "EventCode": "0x22",
+ "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Clear",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR",
+ "BriefDescription": "Write Pending Queue Full Cycles",
+ "EventCode": "0x16",
+ "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD",
+ "BriefDescription": "Write Pending Queue Not Empty",
+ "EventCode": "0x21",
+ "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Read - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD",
+ "BriefDescription": "Write Pending Queue Not Empty",
+ "EventCode": "0x21",
+ "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Write - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR",
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS.PCH0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Write - Set",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR",
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS.PCH1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Clear",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xDE",
- "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR",
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x82",
+ "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.NM_RD",
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x83",
+ "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Read",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.FM_RD",
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Write",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.NM_WR",
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": ": Far Mem Write",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.FM_WR",
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x24",
+ "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": ": Near Mem Read - Clear",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.FM_TGR",
+ "BriefDescription": "Write Pending Queue CAM Match",
+ "EventCode": "0x24",
+ "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
+ "UMask": "0x2",
"Unit": "iMC"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
index 03e99b8aed93..8c09d1358849 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
@@ -1,38557 +1,33727 @@
[
{
- "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "Deprecated": "1",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Remote read requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+ "Deprecated": "1",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+ "Deprecated": "1",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Remote write requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+ "Deprecated": "1",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventName": "UNC_CHA_CLOCKTICKS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "Deprecated": "1",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "Deprecated": "1",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : All Lines Victimized",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x0F",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x0c",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for E-state entries",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for M-state entries",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for S-state entries",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0xC001FF01",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x81",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0xC001FD01",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x81",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0xC80FFD01",
- "UMaskExt": "0xC80FFD",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x81",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0xC817FD01",
- "UMaskExt": "0xC817FD",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0xCCC7FD01",
- "UMaskExt": "0xCCC7FD",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0xC807FD01",
- "UMaskExt": "0xC807FD",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0xC80FFE01",
- "UMaskExt": "0xC80FFE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0xC817FE01",
- "UMaskExt": "0xC817FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0xCCC7FE01",
- "UMaskExt": "0xCCC7FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0xC807FE01",
- "UMaskExt": "0xC807FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0xC001FF04",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x83",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0xC001FD04",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x83",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0xC001FE04",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x83",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0xC001FF01",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0xC001FD01",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0xC001FE01",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0xC80FFE01",
- "UMaskExt": "0xC80FFE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0xC817FE01",
- "UMaskExt": "0xC817FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0xC807FE01",
- "UMaskExt": "0xC807FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0xC001FF04",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0xC001FD04",
- "UMaskExt": "0xC001FD",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0xC001FE04",
- "UMaskExt": "0xC001FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x89",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0xCC43FE04",
- "UMaskExt": "0xCC43FE",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_IIO_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "IIO"
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x89",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x89",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "PortMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8B",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8B",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8B",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x85",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x85",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x85",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "PortMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x87",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x87",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x87",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Lost Forward",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_I_MISC1.LOST_FWD",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Coherent Ops : WbMtoI",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x8D",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x8D",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x8D",
+ "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2e",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Hit : Clean NearMem Read Hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Hit : Dirty NearMem Read Hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the mesh to memory (M2M)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventName": "UNC_M2M_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8F",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8F",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8F",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "CHA to iMC Bypass : Not Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "CHA to iMC Bypass : Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)",
+ "EventName": "UNC_CHA_CLOCKTICKS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_CHA_CMS_CLOCKTICKS",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xf2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xf1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x42",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x41",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x82",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x81",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x22",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x22",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number requests PCIe makes of the main die : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
- "FCMask": "0x07",
+ "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Counter 0 Occupancy",
+ "EventCode": "0x1F",
+ "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6E",
+ "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6E",
+ "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6E",
+ "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Direct GO",
+ "EventCode": "0x6D",
+ "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that did not have to send any snoops because the directory was clean.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that had to send one or more snoops because the directory was not clean.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.HA",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.TOR",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Distress signal asserted : DPT Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Distress signal asserted : DPT Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
- "PortMask": "0x80",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0f",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+ "BriefDescription": "Distress signal asserted : PMM Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound write (fast path) requests received by the IRP",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+ "BriefDescription": "Distress signal asserted : PMM Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : All Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xAF",
+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : All Non Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "EventCode": "0xBA",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x97",
- "Unit": "UPI LL"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : All Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xBA",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : All Non Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
+ "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
"PerPkg": "1",
- "UMask": "0x97",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state.",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
"PerPkg": "1",
+ "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state. : Shared hit and op is RdInvOwn, RdInv, Inv*",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_I_CLOCKTICKS",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
"PerPkg": "1",
- "Unit": "IRP"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FAF RF full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_I_FAF_FULL",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_I_FAF_INSERTS",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests",
+ "EventCode": "0x5E",
+ "EventName": "UNC_CHA_HITME_LOOKUP.READ",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Occupancy of the IRP FAF queue",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_I_FAF_OCCUPANCY",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests",
+ "EventCode": "0x5E",
+ "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FAF allocation -- sent to ADQ",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_I_FAF_TRANSACTIONS",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F and op is RdInvOwn",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M2P_CLOCKTICKS",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInvOwn",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M2P_CMS_CLOCKTICKS",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HtiME$ on Reads without RspFwdI*",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M3UPI_CLOCKTICKS",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
"PerPkg": "1",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of kfclks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_UPI_CLOCKTICKS",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles in L1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_UPI_L1_POWER_CYCLES",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xC88FFD01",
- "UMaskExt": "0xC88FFD",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC897FD01",
- "UMaskExt": "0xC897FD",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xC887FD01",
- "UMaskExt": "0xC887FD",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0xC88FFE01",
- "UMaskExt": "0xC88FFE",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xC897FE01",
- "UMaskExt": "0xC897FE",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC887FE01",
- "UMaskExt": "0xC887FE",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xCC43FD04",
- "UMaskExt": "0xCC43FD",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
- "Counter": "FIXED",
- "CounterType": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_U_CLOCKTICKS",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "Unit": "UBOX"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xCC43FF04",
- "UMaskExt": "0xCC43FF",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC887FF01",
- "UMaskExt": "0xC887FF",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xC807FF01",
- "UMaskExt": "0xC807FF",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0xCCC7FF01",
- "UMaskExt": "0xCCC7FF",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0xC897FF01",
- "UMaskExt": "0xC897FF",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC80FFF01",
- "UMaskExt": "0xC80FFF",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xC807FF01",
- "UMaskExt": "0xC807FF",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0xC817FF01",
- "UMaskExt": "0xC817FF",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
+ "BriefDescription": "Horizontal IV Ring in Use : Left",
+ "EventCode": "0xB9",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0xC80FFF01",
- "UMaskExt": "0xC80FFF",
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
+ "BriefDescription": "Horizontal IV Ring in Use : Right",
+ "EventCode": "0xB9",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x27",
- "Unit": "UPI LL"
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
+ "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
"PerPkg": "1",
- "UMask": "0x27",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
+ "BriefDescription": "HA to iMC Reads Issued : ISOCH",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
"PerPkg": "1",
- "UMask": "0xC816FE01",
- "UMaskExt": "0xC816FE",
+ "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
"PerPkg": "1",
- "UMask": "0xC8177E01",
- "UMaskExt": "0xC8177E",
+ "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
"PerPkg": "1",
- "UMask": "0xC816FE01",
- "UMaskExt": "0xC816FE",
+ "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
"PerPkg": "1",
- "UMask": "0xC8177E01",
- "UMaskExt": "0xC8177E",
+ "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
"PerPkg": "1",
- "UMask": "0xC896FE01",
- "UMaskExt": "0xC896FE",
+ "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
"PerPkg": "1",
- "UMask": "0xC8977E01",
- "UMaskExt": "0xC8977E",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
+ "UMask": "0x1fffff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
+ "BriefDescription": "Cache Lookups : All transactions from Remote Agents",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
"PerPkg": "1",
- "UMask": "0xC806FE01",
- "UMaskExt": "0xC806FE",
+ "PublicDescription": "Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1e20ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
+ "BriefDescription": "Cache Lookups : All Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
"PerPkg": "1",
- "UMask": "0xC8077E01",
- "UMaskExt": "0xC8077E",
+ "PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
"PerPkg": "1",
- "UMask": "0xC886FE01",
- "UMaskExt": "0xC886FE",
+ "UMask": "0x1bd0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL",
"PerPkg": "1",
- "UMask": "0xC8877E01",
- "UMaskExt": "0xC8877E",
+ "UMask": "0x19d0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
+ "BriefDescription": "Cache Lookups : Code Reads",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
"PerPkg": "1",
- "UMask": "0xC8C7FF01",
- "UMaskExt": "0xC8C7FF",
+ "PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
+ "BriefDescription": "Cache Lookups : CRd Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
"PerPkg": "1",
- "UMask": "0xCC57FF01",
- "UMaskExt": "0xCC57FF",
+ "PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
+ "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
"PerPkg": "1",
- "UMask": "0xCD43FF04",
- "UMaskExt": "0xCD43FF",
+ "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
+ "UMask": "0x19d0ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
+ "BriefDescription": "Cache Lookups : Code Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
"PerPkg": "1",
- "UMask": "0xCD43FD04",
- "UMaskExt": "0xCD43FD",
+ "PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd001",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
+ "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket.",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
"PerPkg": "1",
- "UMask": "0xCD43FE04",
- "UMaskExt": "0xCD43FE",
+ "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.",
+ "UMask": "0x1a10ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE",
"PerPkg": "1",
- "UMask": "0xC8178A01",
- "UMaskExt": "0xC8178A",
+ "UMask": "0x1a10ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
+ "BriefDescription": "Cache Lookups : Local request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
"PerPkg": "1",
- "UMask": "0xC8168A01",
- "UMaskExt": "0xC8168A",
+ "PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
"PerPkg": "1",
- "UMask": "0xC8170A01",
- "UMaskExt": "0xC8170A",
+ "UMask": "0x1bc1ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
- "UMask": "0xc867fe01",
- "UMaskExt": "0xc867fe",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x1bc1ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
"PerPkg": "1",
- "UMask": "0xc86ffe01",
- "UMaskExt": "0xc86ffe",
+ "UMask": "0x1fc1ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
+ "BriefDescription": "Cache Lookups : Data Read Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
"PerPkg": "1",
- "UMask": "0xC8178A01",
- "UMaskExt": "0xC8178A",
+ "PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions.",
"Unit": "CHA"
},
{
- "BriefDescription": "Free running counter that increments for IIO clocktick",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x19c1ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.TO_PMM",
+ "BriefDescription": "Cache Lookups : Data Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
"PerPkg": "1",
- "UMask": "0x0720",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bc101",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE",
"PerPkg": "1",
- "UMask": "0x1C80",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x1a01ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
"PerPkg": "1",
- "UMask": "0xCCD7FE01",
- "UMaskExt": "0xCCD7FE",
+ "UMask": "0x841ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
+ "BriefDescription": "Cache Lookups : E State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.E",
"PerPkg": "1",
- "UMask": "0xC8F3FE04",
- "UMaskExt": "0xC8F3FE",
+ "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
+ "BriefDescription": "Cache Lookups : F State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.F",
"PerPkg": "1",
- "UMask": "0xc8f3fe04",
- "UMaskExt": "0xc8f3fe",
+ "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
+ "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
"PerPkg": "1",
- "UMask": "0xC8178601",
- "UMaskExt": "0xC81786",
+ "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1a44ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
+ "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL",
"PerPkg": "1",
- "UMask": "0xC8168601",
- "UMaskExt": "0xC81686",
+ "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1844ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
+ "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket.",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE",
"PerPkg": "1",
- "UMask": "0xC8170601",
- "UMaskExt": "0xC81706",
+ "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1a04ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
+ "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
"PerPkg": "1",
- "UMask": "0xC8178601",
- "UMaskExt": "0xC81786",
+ "PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
+ "BriefDescription": "Cache Lookups : I State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.I",
"PerPkg": "1",
- "UMask": "0xC8F3FD04",
- "UMaskExt": "0xC8F3FD",
+ "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
"PerPkg": "1",
- "UMask": "0xC8F3FF04",
- "UMaskExt": "0xC8F3FF",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
+ "UMask": "0x189dff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
+ "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F",
"PerPkg": "1",
- "UMask": "0xCCD7FF01",
- "UMaskExt": "0xCCD7FF",
+ "PublicDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL",
"PerPkg": "1",
- "UMask": "0xC8F3FF04",
- "UMaskExt": "0xC8F3FF",
+ "UMask": "0x189dff",
"Unit": "CHA"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM",
+ "Deprecated": "1",
"EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
"PerPkg": "1",
- "UMask": "0x1BC1FF",
- "UMaskExt": "0x1BC1",
+ "UMask": "0xbdfff",
"Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Transactions homed locally",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.",
+ "UMask": "0xbdfff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : M State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.M",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : All Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1fe001",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Write Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remote non-snoop request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remote non-snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Non-snoop transactions to the LLC from remote agent",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Reads",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd9ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x9d9ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x11d9ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd901",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0xbd901",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x13d901",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x161901",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0xa19ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bd90e",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
- "FCMask": "0x04",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x15dfff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+ "BriefDescription": "Cache Lookups : Transactions homed remotely Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F",
"PerPkg": "1",
- "UMask": "0x78",
- "Unit": "IRP"
+ "PublicDescription": "Cache Lookups : Transactions homed remotely Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
- "FCMask": "0x04",
+ "BriefDescription": "Cache Lookups : Remote snoop request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F",
"PerPkg": "1",
- "PortMask": "0xff",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Cache Lookups : Remote snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Snoop transactions to the LLC from remote agent",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
- "FCMask": "0x04",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
"PerPkg": "1",
- "UMask": "0xff",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
+ "UMask": "0x1c19ff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
+ "BriefDescription": "Cache Lookups : Transactions homed remotely",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM",
"PerPkg": "1",
- "UMask": "0xCC42FF04",
- "UMaskExt": "0xCC42FF",
+ "PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
+ "UMask": "0x15dfff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
+ "BriefDescription": "Cache Lookups : RFO Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
"PerPkg": "1",
- "UMask": "0xCC437F04",
- "UMaskExt": "0xCC437F",
+ "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
+ "UMask": "0x1bc8ff",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
+ "BriefDescription": "Cache Lookups : RFO Request Filter",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
"PerPkg": "1",
- "UMask": "0xCD42FF04",
- "UMaskExt": "0xCD42FF",
+ "PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
+ "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
"PerPkg": "1",
- "UMask": "0xCD437F04",
- "UMaskExt": "0xCD437F",
+ "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
+ "UMask": "0x19c8ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+ "BriefDescription": "Cache Lookups : RFO Misses",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.",
+ "UMask": "0x1bc801",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x888ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.HA",
+ "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket.",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.",
+ "UMask": "0x1a08ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline directory state updates : Directory Updated memory write from TOR pipe",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.TOR",
+ "BriefDescription": "Cache Lookups : S State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.S",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
+ "BriefDescription": "Cache Lookups : SnoopFilter - E State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - All Lines",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+ "BriefDescription": "Cache Lookups : SnoopFilter - H State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
"PerPkg": "1",
- "UMask": "0x200F",
- "UMaskExt": "0x20",
+ "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote - All Lines",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+ "BriefDescription": "Cache Lookups : SnoopFilter - S State",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
"PerPkg": "1",
- "UMask": "0x800F",
- "UMaskExt": "0x80",
+ "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR",
+ "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.",
+ "UMask": "0x1a42ff",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
"Deprecated": "1",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x842ff",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
"Deprecated": "1",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x17c2ff",
"Unit": "CHA"
},
{
- "BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+ "BriefDescription": "Lines Victimized : All Lines Victimized",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
"PerPkg": "1",
+ "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0xf",
"Unit": "CHA"
},
{
- "BriefDescription": "Number of times that an RFO hit in S state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RFO_HIT_S",
+ "BriefDescription": "Lines Victimized : Lines in E state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE",
+ "BriefDescription": "Lines Victimized : Local - All Lines",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
"PerPkg": "1",
- "UMask": "0x30",
+ "PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x200f",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Lines Victimized : Local - Lines in E State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2002",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
+ "BriefDescription": "Lines Victimized : Local - Lines in M State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2001",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspIFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
+ "BriefDescription": "Lines Victimized : Local Only",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
+ "BriefDescription": "Lines Victimized : Local - Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2004",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspSFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
+ "BriefDescription": "Lines Victimized : Lines in M state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL",
+ "BriefDescription": "Lines Victimized : Remote - All Lines",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
"PerPkg": "1",
- "UMask": "0xC001FFff",
- "UMaskExt": "0xC001FF",
+ "PublicDescription": "Lines Victimized : Remote - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x800f",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD",
+ "BriefDescription": "Lines Victimized : Remote - Lines in E State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
"PerPkg": "1",
- "UMask": "0xcccffd01",
- "UMaskExt": "0xcccffd",
+ "PublicDescription": "Lines Victimized : Remote - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8002",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD",
+ "BriefDescription": "Lines Victimized : Remote - Lines in M State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
"PerPkg": "1",
- "UMask": "0xccd7fd01",
- "UMaskExt": "0xccd7fd",
+ "PublicDescription": "Lines Victimized : Remote - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8001",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "BriefDescription": "Lines Victimized : Remote Only",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY",
"PerPkg": "1",
- "UMask": "0xC80FFD01",
- "UMaskExt": "0xC80FFD",
+ "PublicDescription": "Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+ "BriefDescription": "Lines Victimized : Remote - Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
"PerPkg": "1",
- "UMask": "0xC817FD01",
- "UMaskExt": "0xC817FD",
+ "PublicDescription": "Lines Victimized : Remote - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8004",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
+ "BriefDescription": "Lines Victimized : Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
- "UMask": "0xCCC7FD01",
- "UMaskExt": "0xCCC7FD",
+ "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+ "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
"PerPkg": "1",
- "UMask": "0xC807FD01",
- "UMaskExt": "0xC807FD",
+ "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
+ "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
"PerPkg": "1",
- "UMask": "0xCCC7FE01",
- "UMaskExt": "0xCCC7FE",
+ "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+ "BriefDescription": "Number of times that an RFO hit in S state.",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RFO_HIT_S",
"PerPkg": "1",
- "UMask": "0xc803fe04",
- "UMaskExt": "0xc803fe",
+ "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+ "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "UMask": "0xc803fe04",
- "UMaskExt": "0xc803fe",
+ "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+ "BriefDescription": "Cbo Misc : Write Combining Aliasing",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.WC_ALIASING",
"PerPkg": "1",
- "UMask": "0xcc43fe04",
- "UMaskExt": "0xcc43fe",
+ "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "EventCode": "0xE6",
+ "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "EventCode": "0xE6",
+ "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Local Rd",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.LOCAL_READ",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Off",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Remote Rd",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.REMOTE_READ",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : Hit M",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.RFO",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles when Direct2UPI was Disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.NI",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
"PerPkg": "1",
- "UMaskExt": "0x1E",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tag Miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M2M_TAG_MISS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass : Not Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to core transaction was overridden",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ALL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI",
"PerPkg": "1",
- "UMask": "0x0704",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.NORMAL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH",
"PerPkg": "1",
- "UMask": "0x0701",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.ALL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM",
"PerPkg": "1",
- "UMask": "0x1C10",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
"PerPkg": "1",
- "UMask": "0x1C01",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
"PerPkg": "1",
- "UMask": "0x1C02",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x01",
- "EventName": "UNC_M2M_RxC_AD_INSERTS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_M2M_RxC_BL_INSERTS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x06",
- "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x09",
- "EventName": "UNC_M2M_TxC_AD_INSERTS",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0A",
- "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI",
+ "BriefDescription": "Pipe Rejects",
+ "EventCode": "0x42",
+ "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass : Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass : Not Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "EventCode": "0x65",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE",
+ "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the LLC.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single External Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+ "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the SF.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single Core Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+ "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due to a pending read to the same near memory set in the TOR.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Single Eviction",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
"PerPkg": "1",
- "UMask": "0x81",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
"PerPkg": "1",
- "UMask": "0xF1",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "EventCode": "0x70",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
"PerPkg": "1",
- "UMask": "0x22",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
"PerPkg": "1",
- "UMask": "0x22",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ",
"PerPkg": "1",
- "UMask": "0x42",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
"PerPkg": "1",
- "UMask": "0x82",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+ "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT",
"PerPkg": "1",
- "UMask": "0xF2",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC",
+ "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.THROTTLE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C",
+ "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD",
+ "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+ "EventCode": "0x66",
+ "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP",
+ "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+ "EventCode": "0x67",
+ "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": ": count # of FAST TOR Request inserted to ha_tor_req_fifo",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL",
+ "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
+ "EventCode": "0x67",
+ "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": ": count # of SLOW TOR Request inserted to ha_pmm_tor_req_fifo",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.GO",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Direct GO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
"PerPkg": "1",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_CHA_HITME_LOOKUP.READ",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+ "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x30",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+ "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
+ "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
+ "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .",
+ "UMask": "0x3",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HtiME$ on Reads without RspFwdI*",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
+ "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "HA to iMC Reads Issued : ISOCH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+ "BriefDescription": "Remote read requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+ "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0xc",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+ "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+ "BriefDescription": "Remote write requests sent to the CHA's home agent",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Lines in M state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Lines in E state",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Lines in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local Only",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "EventCode": "0xAC",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote Only",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMaskExt": "0x80",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - Lines in M State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x2001",
- "UMaskExt": "0x20",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - Lines in E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x2002",
- "UMaskExt": "0x20",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Local - Lines in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x2004",
- "UMaskExt": "0x20",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote - Lines in M State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x8001",
- "UMaskExt": "0x80",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote - Lines in E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x8002",
- "UMaskExt": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized : Remote - Lines in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x8004",
- "UMaskExt": "0x80",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : Silent Snoop Eviction",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : Write Combining Aliasing",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.WC_ALIASING",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : CV0 Prefetch Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc : CV0 Prefetch Miss",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+ "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Local InvItoE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Local Rd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.LOCAL_READ",
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Remote Rd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.REMOTE_READ",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_CHA_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast : Off",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
+ "BriefDescription": "Ingress (from CMS) Allocations : IPQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH",
+ "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH",
+ "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP",
+ "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH",
+ "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV",
+ "BriefDescription": "Ingress (from CMS) Allocations : RRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE",
+ "BriefDescription": "Ingress (from CMS) Allocations : WBQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x10",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x40",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x80",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x100",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMaskExt": "0x200",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMaskExt": "0x800",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
"PerPkg": "1",
- "UMaskExt": "0x1000",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMaskExt": "0x2000",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMaskExt": "0x4000",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMaskExt": "0x8000",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMaskExt": "0x10000",
+ "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH",
+ "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMaskExt": "0x20000",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMaskExt": "0x40000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x80000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x100000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x200000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMaskExt": "0x400000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x800000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x1000000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x2000000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMaskExt": "0x4000000",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMaskExt": "0x8000000",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
"PerPkg": "1",
- "UMaskExt": "0x10000000",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC0",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC1",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC2",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC3",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC4",
+ "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC5",
+ "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC6",
+ "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC7",
+ "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC8",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC9",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC10",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC11",
+ "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMaskExt": "0x08",
+ "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC12",
+ "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMaskExt": "0x10",
+ "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC13",
+ "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : IRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+ "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : IPQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : PRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : RRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations : WBQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
+ "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
"PerPkg": "1",
+ "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "ISMQ Rejects - Set 1 : HA",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "ISMQ Retries - Set 1 : HA",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "Ingress (from CMS) Occupancy : IPQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Ingress (from CMS) Occupancy : RRQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Ingress (from CMS) Occupancy : WBQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
+ "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+ "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "Other Retries - Set 1 : ANY0",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "Other Retries - Set 1 : HA",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "Other Retries - Set 1 : LLC Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Other Retries - Set 1 : SF Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+ "BriefDescription": "Other Retries - Set 1 : Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+ "PerPkg": "1",
+ "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+ "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+ "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+ "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+ "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+ "BriefDescription": "Request Queue Retries - Set 1 : HA",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy : IRQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy : IPQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
+ "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy : RRQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
+ "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy : WBQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
+ "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "Request Queue Retries - Set 1 : Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+ "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+ "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+ "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+ "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "BriefDescription": "RRQ Rejects - Set 1 : ANY0",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+ "BriefDescription": "RRQ Rejects - Set 1 : HA",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+ "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+ "BriefDescription": "RRQ Rejects - Set 1 : SF Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "RRQ Rejects - Set 1 : Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+ "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+ "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "WBQ Rejects - Set 1 : ANY0",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "WBQ Rejects - Set 1 : HA",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
+ "PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
"PerPkg": "1",
+ "PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "BriefDescription": "WBQ Rejects - Set 1 : SF Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "BriefDescription": "WBQ Rejects - Set 1 : Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "BriefDescription": "Transgress Ingress Bypass : AK",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
+ "EventCode": "0xE2",
+ "EventName": "UNC_CHA_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "Transgress Injection Starvation : AK",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
+ "BriefDescription": "Transgress Injection Starvation : IV",
+ "EventCode": "0xE3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "Transgress Ingress Allocations : AK",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
- "PerPkg": "1",
- "UMask": "0x04",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
+ "PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
+ "EventCode": "0xE1",
+ "EventName": "UNC_CHA_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Transgress Ingress Occupancy : AK",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : ANY0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : HA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : SF Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : Victim",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
+ "EventCode": "0xE0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+ "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+ "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
- "PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests",
"UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : Broadcast snoops for Remote Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to remote requests",
"UMask": "0x20",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : Directed snoops for Local Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "Snoops Sent : Directed snoops for Remote Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x51",
"EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to remote requests",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : Rsp*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPWB",
+ "BriefDescription": "Snoops Sent : Snoops sent for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB",
+ "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Snoops Sent : Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to remote requests",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "Snoop Responses Received : RSPCNFLCT*",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "Snoop Responses Received : RspFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x5C",
"EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+ "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+ "BriefDescription": "Snoop Responses Received : RspI",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspIFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+ "BriefDescription": "Snoop Responses Received : RspIFwd",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : RspSFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "BriefDescription": "Snoop Responses Received : RspS",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
+ "BriefDescription": "Snoop Responses Received : RspSFwd",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
+ "BriefDescription": "Snoop Responses Received : Rsp*WB",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPWB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
"BriefDescription": "Snoop Responses Received Local : RspCnflct",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "Snoop Responses Received Local : RspFwd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x5D",
"EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
+ "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
+ "BriefDescription": "Snoop Responses Received Local : RspI",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
+ "BriefDescription": "Snoop Responses Received Local : RspIFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
+ "BriefDescription": "Snoop Responses Received Local : RspS",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
+ "BriefDescription": "Snoop Responses Received Local : RspSFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Snoop Responses Received Local : Rsp*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM",
"EventCode": "0x6B",
- "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI : Pushed to LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+ "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI : Pushed to Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+ "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
+ "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
+ "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
+ "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF",
+ "EventCode": "0x6B",
+ "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMaskExt": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
- "UMaskExt": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
- "UMaskExt": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMaskExt": "0x08",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMaskExt": "0x10",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMaskExt": "0x20",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Sent (on 0?)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.SENT0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Sent (on 1?)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.SENT1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "PortMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x10",
- "Unit": "IIO"
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD1",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD1",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD1",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD3",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD3",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD3",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD5",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD5",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD5",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD7",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD7",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD7",
+ "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ffff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DDR4 Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.DDR",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : SF/LLC Evictions",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : Just Hits",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.HIT",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8d7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; CRd Pref from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0xcccffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0xccd7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB lookups first",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB lookups all",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Hits to a 4K Page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.4K_HITS",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Hits to a 2M Page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.2M_HITS",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Hits to a 1G Page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.1G_HITS",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.MISSES",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Context cache lookups",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Context cache hits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": PageWalk cache lookup",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": IOMMU memory access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Cycles PWT full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Interrupt Entry cache lookup",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": ": Interrupt Entry cache hit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x10",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x20",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccfff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817fe01",
+ "Unit": "CHA"
},
- {
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
- "FCMask": "0x07",
+ {
+ "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8178601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc816fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8178a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc896fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; DRd Pref misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter",
+ "UMask": "0xc8977e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8177e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc867fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8678a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
"PerPkg": "1",
- "PortMask": "0x40",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
- "FCMask": "0x07",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
"PerPkg": "1",
- "PortMask": "0x80",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Total Write Cache Occupancy : Any Source",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0F",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Total Write Cache Occupancy : Snoops",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0F",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Coherent Ops : CLFlush",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_I_IRP_ALL.EVICTS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1e",
- "EventName": "UNC_I_MISC0.FAST_REQ",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.FAST_REJ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1e",
- "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1e",
- "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers >From Primary to Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.FAST_XFER",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints >From Primary to Secondary",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+ "BriefDescription": "TOR Inserts; WCiL misses from local IA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f0a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_I",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_S",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_E",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1f",
- "EventName": "UNC_I_MISC1.SLOW_M",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc806fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Received Invalid",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Misc Events - Set 1 : Received Valid",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc886fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : P2P reads",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8877e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : P2P Writes",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8077e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : P2P Message",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+ "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : P2P completions",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+ "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc877de01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : Match if remote only",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : match if remote and target matches",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+ "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : match if local only",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "P2P Transactions : match if local and target matches",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+ "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : Miss",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.MISS",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : Hit I",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : Hit E or S",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc87fde01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : SnpCode",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : SnpData",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+ "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses : SnpInv",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+ "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound Transaction Count : Writes",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IRP"
+ "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc3fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound Transaction Count : Atomic",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+ "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc37ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound Transaction Count : Other",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc2fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound Transaction Count : Select Source",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+ "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc27ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass : Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
+ "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc67ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass : Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+ "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass : Not Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+ "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On Dirty Line in I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+ "BriefDescription": "TOR Inserts : All requests from IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On Dirty Line in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+ "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On Dirty Line in L State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+ "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On Dirty Line in A State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On NonDirty Line in I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On NonDirty Line in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+ "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On NonDirty Line in L State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+ "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit : On NonDirty Line in A State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On Dirty Line in I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On Dirty Line in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd42ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On Dirty Line in L State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd437f04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On Dirty Line in A State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc42ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On NonDirty Line in I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc437f04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On NonDirty Line in S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+ "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On NonDirty Line in L State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+ "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss : On NonDirty Line in A State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+ "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
+ "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x0101",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
+ "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x0102",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
+ "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x0104",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
+ "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
"PerPkg": "1",
- "UMask": "0x0140",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
+ "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
"PerPkg": "1",
- "UMask": "0x0201",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc23ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
+ "BriefDescription": "TOR Inserts : IPQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x0202",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
+ "BriefDescription": "TOR Inserts : IRQ - iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
"PerPkg": "1",
- "UMask": "0x0204",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
+ "BriefDescription": "TOR Inserts : IRQ - Non iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
"PerPkg": "1",
- "UMask": "0x0240",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR",
+ "BriefDescription": "TOR Inserts : Just ISOC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
"PerPkg": "1",
- "UMask": "0x0440",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
+ "BriefDescription": "TOR Inserts : Just Local Targets",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
"PerPkg": "1",
- "UMask": "0x0401",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
+ "BriefDescription": "TOR Inserts : All from Local iA and IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x0402",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+ "UMask": "0xc000ff05",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
+ "BriefDescription": "TOR Inserts : All from Local iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
"PerPkg": "1",
- "UMask": "0x0404",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+ "UMask": "0xc000ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
+ "BriefDescription": "TOR Inserts : All from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
"PerPkg": "1",
- "UMask": "0x0408",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+ "UMask": "0xc000ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
+ "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
"PerPkg": "1",
- "UMask": "0x0410",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
+ "BriefDescription": "TOR Inserts : Just Misses",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MISS",
"PerPkg": "1",
- "UMaskExt": "0x05",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_NI",
+ "BriefDescription": "TOR Inserts : MMCFG Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
"PerPkg": "1",
- "UMaskExt": "0x06",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
+ "BriefDescription": "TOR Inserts : Just NearMem",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
"PerPkg": "1",
- "UMask": "0x0801",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
+ "BriefDescription": "TOR Inserts : Just NonCoherent",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
"PerPkg": "1",
- "UMask": "0x0802",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
+ "BriefDescription": "TOR Inserts : Just NotNearMem",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
"PerPkg": "1",
- "UMask": "0x0804",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
+ "BriefDescription": "TOR Inserts : PMM Access",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PMM",
"PerPkg": "1",
- "UMask": "0x0808",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PMM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
+ "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
"PerPkg": "1",
- "UMask": "0x0810",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
+ "BriefDescription": "TOR Inserts : PRQ - IOSF",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
"PerPkg": "1",
- "UMaskExt": "0x09",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_NI",
+ "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
"PerPkg": "1",
- "UMaskExt": "0x0A",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Packet Header Matches : Mesh Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MESH",
+ "BriefDescription": "TOR Inserts : Just Remote Targets",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Packet Header Matches : MC Match",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MC",
+ "BriefDescription": "TOR Inserts : RRQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
+ "BriefDescription": "TOR Inserts : WBQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
+ "BriefDescription": "TOR Occupancy : DDR4 Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2",
+ "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
+ "BriefDescription": "TOR Occupancy : Just Hits",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
+ "BriefDescription": "TOR Occupancy : All requests from iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2",
+ "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Full : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_FULL.CH0",
+ "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8d7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Full : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_FULL.CH1",
+ "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Full : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_FULL.CH2",
+ "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc88fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+ "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_NE.CH0",
+ "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_NE.CH1",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_NE.CH2",
+ "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.NDR",
+ "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+ "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
+ "PerPkg": "1",
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897fd01",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+ "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccffd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+ "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+ "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fd01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
"PerPkg": "1",
- "UMask": "0x88",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x90",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd47ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+ "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0xA0",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccfff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+ "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+ "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+ "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+ "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+ "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88efe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+ "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc88f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+ "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc80f7e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc817fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+ "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc837fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8178601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc816fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8168a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc827fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8a7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8178a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc897fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+ "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc896fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8968a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8978a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+ "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
+ "UMask": "0xc8977e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
+ "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8970a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8177e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8170a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc867fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Full : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8678a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+ "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc47fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcccffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccd7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xccc7fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "WPQ Flush : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "WPQ Flush : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8668a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "WPQ Flush : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M2M_WPQ_FLUSH.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86e8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86e8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
+ "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter",
+ "UMask": "0xc86f0a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full : Mirror",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8670a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f0a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Inserts : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc806fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.CH2",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc886fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8877e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x63",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8077e01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x63",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
+ "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC: For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x63",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2",
+ "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc877de01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x62",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86ffe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x62",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867fe01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x62",
- "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8678a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8601",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86f8a01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy : Mirror",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
+ "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc87fde01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc807ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
+ "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc887ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Inserts : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2",
+ "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc57ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
+ "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc27ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
+ "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc86fff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Posted Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2",
+ "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc867ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
+ "BriefDescription": "TOR Occupancy : All requests from IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
+ "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8c3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
+ "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
+ "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
+ "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fd04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
+ "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc001fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
+ "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
+ "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcd43fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
+ "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
+ "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803fe04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
+ "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc8f3ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
+ "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xc803ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
+ "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0xcc23ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
+ "BriefDescription": "TOR Occupancy : IPQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
+ "BriefDescription": "TOR Occupancy : IRQ - iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
+ "BriefDescription": "TOR Occupancy : IRQ - Non iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.ALL",
+ "BriefDescription": "TOR Occupancy : Just ISOC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+ "BriefDescription": "TOR Occupancy : Just Local Targets",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+ "BriefDescription": "TOR Occupancy : All from Local iA and IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests",
+ "UMask": "0xc000ff05",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+ "BriefDescription": "TOR Occupancy : All from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores",
+ "UMask": "0xc000ff01",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+ "BriefDescription": "TOR Occupancy : All from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic",
+ "UMask": "0xc000ff04",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+ "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+ "BriefDescription": "TOR Occupancy : Just Misses",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+ "BriefDescription": "TOR Occupancy : MMCFG Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
+ "BriefDescription": "TOR Occupancy : Just NearMem",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
+ "BriefDescription": "TOR Occupancy : Just NonCoherent",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
+ "BriefDescription": "TOR Occupancy : Just NotNearMem",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
+ "BriefDescription": "TOR Occupancy : PMM Access",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
+ "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
+ "BriefDescription": "TOR Occupancy : PRQ - IOSF",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
+ "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
+ "BriefDescription": "TOR Occupancy : Just Remote Targets",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress (to CMS) Ingress",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CBox AD Credits Empty : VNA Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CBox AD Credits Empty : Writebacks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CBox AD Credits Empty : Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CBox AD Credits Empty : Snoops",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+ "BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AD - Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AD - Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AD - Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : BL - Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AK - Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi Slot Flit Received : AK - Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN0 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Lost Arb for VN1 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Arb Miscellaneous : Max Parallel Win",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN0 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "No Credits to Arb for VN1 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
- {
- "BriefDescription": "Can't Arb for VN0 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ",
+ {
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN0 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Can't Arb for VN1 : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Miscellaneous Credit Events",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : VNA In Use",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : Packets in BGF FIFO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : Packets in BGF Path",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : Transmit Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : D2K Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Credit Occupancy : Credits Consumed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "EventCode": "0x95",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "EventCode": "0x97",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : TSV High",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : No BGF Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Flit Not Sent : No TxQ Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "EventCode": "0x99",
+ "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Accumulate",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Parallel Ok",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Parallel Message",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : One Message",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : Two Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : Three Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : One Message in non-VNA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : One Slot Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : Two Slots Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sent Header Flit : All Slots Taken",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : TSV High",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : Cycle valid for Flit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : No BGF Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : No TxQ Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD",
+ "BriefDescription": "Vertical IV Ring in Use : Down",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : VN0",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.VN0",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : VN1",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.VN1",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : Parallel Attempt",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : Parallel Success",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
+ "BriefDescription": "WbPushMtoI : Pushed to LLC",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : Can't Slot AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
+ "BriefDescription": "WbPushMtoI : Pushed to Memory",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Message Held : Can't Slot BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
+ "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
+ "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
+ "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
+ "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
+ "BriefDescription": "XPT Prefetches : Sent (on 0?)",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.SENT0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
+ "BriefDescription": "XPT Prefetches : Sent (on 1?)",
+ "EventCode": "0x6f",
+ "EventName": "UNC_CHA_XPT_PREF.SENT1",
"PerPkg": "1",
+ "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "CHA"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : REQ on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : SNP on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : RSP on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : RSP on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : WB on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : NCB on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 message can't slot into flit : NCS on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
+ "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
+ "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : REQ on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
+ "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller",
+ "EventCode": "0x01",
+ "EventName": "UNC_IIO_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz)",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : SNP on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
+ "BriefDescription": "Free running counter that increments for IIO clocktick",
+ "EventName": "UNC_IIO_CLOCKTICKS_FREERUN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : RSP on AD",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
+ "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0xFF",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : RSP on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0xff",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : WB on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : NCB on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 message can't slot into flit : NCS on BL",
- "Counter": "0,1,2",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Corrected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Level < 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Level < 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Level < 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
+ "FCMask": "0x04",
+ "PerPkg": "1",
+ "PortMask": "0x40",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
+ "UMask": "0x3",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Level < 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+ "UMask": "0xff",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Remote VNA Credits : Any In Use",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
+ "UMask": "0xff",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
+ "FCMask": "0x04",
"PerPkg": "1",
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
+ "FCMask": "0x04",
"PerPkg": "1",
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
+ "FCMask": "0x04",
"PerPkg": "1",
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+ "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7",
+ "EventCode": "0xd5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
+ "FCMask": "0x04",
"PerPkg": "1",
+ "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7",
"UMask": "0x80",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for AD : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN0 NCB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN0 NCS Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN1 NCS Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Failed ARB for BL : VN1 NCB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
+ "EventCode": "0xc0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
+ "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
- "CounterType": "PGMABLE",
- "EventCode": "0x1F",
- "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VNA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VNA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+ "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 Credit Used : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN0 No Credits : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
+ "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 Credit Used : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : REQ on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : SNP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : RSP on AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : RSP on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : WB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "VN1 No Credits : NCB on BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x81",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x82",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x84",
- "Unit": "M3UPI"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x90",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xA0",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7E",
- "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC0",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+ "BriefDescription": "Data requested of the CPU : Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
"UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7D",
- "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M3UPI"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.ARB",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : VLW",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : MSI",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : IPI",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UBOX"
+ "PortMask": "0x100",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : Doorbell",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UBOX"
+ "PortMask": "0x200",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Message Received : Interrupt",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UBOX"
+ "PortMask": "0x01",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "PortMask": "0x02",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDRAND",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "PortMask": "0x04",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDSEED",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "PortMask": "0x08",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UBOX"
+ "PortMask": "0x10",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Direct packet attempts : D2C",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0x20",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Direct packet attempts : D2K",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0x40",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0x80",
+ "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "BriefDescription": "Incoming arbitration requests : Passing data to be written",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "BriefDescription": "Incoming arbitration requests : Request Ownership",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "BriefDescription": "Incoming arbitration requests : Writing line",
+ "EventCode": "0x86",
+ "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "BriefDescription": "Incoming arbitration requests granted : Writing line",
+ "EventCode": "0x87",
+ "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0xFF",
+ "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "BriefDescription": ": IOTLB Hits to a 1G Page",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.1G_HITS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "BriefDescription": ": IOTLB Hits to a 2M Page",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.2M_HITS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "BriefDescription": ": IOTLB Hits to a 4K Page",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.4K_HITS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "BriefDescription": ": IOTLB lookups all",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "BriefDescription": ": Context cache hits",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "BriefDescription": ": Context cache lookups",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "BriefDescription": ": IOTLB lookups first",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "BriefDescription": ": IOTLB Fills (same as IOTLB miss)",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_IOMMU0.MISSES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "BriefDescription": ": Cycles PWT full",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "BriefDescription": ": IOMMU memory access",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "BriefDescription": ": PWC Hit to a 1G page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+ "BriefDescription": ": PWC Hit to a 2M page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
+ "BriefDescription": ": PWC Hit to a 4K page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
"PerPkg": "1",
- "UMask": "0x108",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+ "BriefDescription": ": PWT Hit to a 256T page",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
"PerPkg": "1",
- "UMask": "0x09",
- "Unit": "UPI LL"
+ "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
+ "BriefDescription": ": PageWalk cache fill",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
"PerPkg": "1",
- "UMask": "0x109",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": ": PageWalk cache lookup",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x0A",
- "Unit": "UPI LL"
+ "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "BriefDescription": ": Interrupt Entry cache hit",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
"PerPkg": "1",
- "UMask": "0x10A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+ "BriefDescription": ": Interrupt Entry cache lookup",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
"PerPkg": "1",
- "UMask": "0x0C",
- "Unit": "UPI LL"
+ "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "BriefDescription": ": Device-selective Context cache invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
"PerPkg": "1",
- "UMask": "0x10C",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+ "BriefDescription": ": Domain-selective Context cache invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
"PerPkg": "1",
- "UMask": "0x0D",
- "Unit": "UPI LL"
+ "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
+ "BriefDescription": ": Context cache global invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
"PerPkg": "1",
- "UMask": "0x10D",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
"PerPkg": "1",
- "UMask": "0x0E",
- "Unit": "UPI LL"
+ "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": ": Global IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
"PerPkg": "1",
- "UMask": "0x10E",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": ": Page-selective IOTLB invalidation cycles",
+ "EventCode": "0x43",
+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
"PerPkg": "1",
- "UMask": "0x10F",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
- {
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
+ {
+ "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x1AA",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
+ "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x12A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+ "BriefDescription": "AND Mask/match for debug bus : PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+ "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+ "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
+ "EventCode": "0x02",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : PCIE bus",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.DATA",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
"PerPkg": "1",
+ "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)",
"EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.NULL",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
+ "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match",
"UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : LLCTRL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+ "BriefDescription": "Counting disabled",
+ "EventCode": "0x80",
+ "EventName": "UNC_IIO_NOTHING",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Protocol Header",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+ "BriefDescription": "Occupancy of outbound request queue : To device",
+ "EventCode": "0xC5",
+ "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_UPI_RxL_FLITS.IDLE",
+ "BriefDescription": ": Passing data to be written",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x47",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": ": Passing data to be written : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+ "BriefDescription": ": Issuing final read or write of line",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+ "BriefDescription": ": Processing response from IOMMU",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+ "BriefDescription": ": Issuing to IOMMU",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+ "BriefDescription": ": Request Ownership",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": ": Request Ownership : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+ "BriefDescription": ": Writing line",
+ "EventCode": "0x88",
+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": ": Writing line : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+ "BriefDescription": "Number requests sent to PCIe from main die : >From IRP",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "BriefDescription": "Number requests sent to PCIe from main die : >From ITC",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
+ "EventCode": "0xc2",
+ "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "BriefDescription": "Number requests PCIe makes of the main die : Drop request",
+ "EventCode": "0x85",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "BriefDescription": "Number requests PCIe makes of the main die : All",
+ "EventCode": "0x85",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "BriefDescription": "Num requests sent by PCIe - by target : Abort",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0xFF",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0xFF",
"UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0xFF",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Num requests sent by PCIe - by target : Memory",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
+ "EventCode": "0x8E",
+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "BriefDescription": "ITC address map 1",
+ "EventCode": "0x8F",
+ "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
+ "EventCode": "0xD0",
+ "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
+ "EventCode": "0xD1",
+ "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "BriefDescription": "PWT occupancy",
+ "EventCode": "0x42",
+ "EventName": "UNC_IIO_PWT_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
+ "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
+ "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x108",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
+ "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x09",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
+ "BriefDescription": "PCIe Request - cacheline complete : Writing line",
+ "EventCode": "0x91",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x109",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": "PCIe Request complete : Passing data to be written",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0A",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
+ "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0C",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10C",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
+ "BriefDescription": "PCIe Request complete : Request Ownership",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0D",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
+ "BriefDescription": "PCIe Request complete : Writing line",
+ "EventCode": "0x92",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10D",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0E",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10E",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": "PCIe Request - pass complete : Request Ownership",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "PCIe Request - pass complete : Writing line",
+ "EventCode": "0x90",
+ "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10F",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0xFF",
+ "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
+ "BriefDescription": "Symbol Times on Link",
+ "EventCode": "0x82",
+ "EventName": "UNC_IIO_SYMBOL_TIMES",
"PerPkg": "1",
- "UMask": "0x1AA",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x12A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Slot 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Slot 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Slot 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Data",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.DATA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.NULL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : LLCTRL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
"UMask": "0x40",
- "Unit": "UPI LL"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Protocol Header",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Valid Flits Sent : Idle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_UPI_TxL_FLITS.IDLE",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x47",
- "Unit": "UPI LL"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : I State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.I",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : SnoopFilter - S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.SF_S",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : SnoopFilter - E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.SF_E",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : SnoopFilter - H State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.SF_H",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : S State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.S",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : E State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.E",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : M State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.M",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : F State",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.F",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache Lookups : RFO Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1BC8FF",
- "UMaskExt": "0x1BC8",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : IRQ - iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : SF/LLC Evictions",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : PRQ - IOSF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : IPQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : IRQ - Non iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : PRQ - Non IOSF",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : RRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.RRQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : WBQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.WBQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
"UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : All from Local IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF04",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : All from Local iA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF01",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : All from Local iA and IO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF05",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just Hits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.DDR4",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : MMCFG Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MMCFG",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just Local Targets",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just Remote Targets",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x100",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x200",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x400",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just NearMem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x400000",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just NotNearMem",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x800000",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just NonCoherent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.NONCOH",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x1000000",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts : Just ISOC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ISOC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x2000000",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : IRQ - iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : SF/LLC Evictions",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : PRQ - IOSF",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : IPQ",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : IRQ - Non iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : PRQ - Non IOSF",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Local IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF04",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Local iA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF01",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : All from Local iA and IO",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xC000FF05",
- "UMaskExt": "0xC000FF",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Hits",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Misses",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : MMCFG Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Local Targets",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just Remote Targets",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x100",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x200",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x400",
- "Unit": "CHA"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just NearMem",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM",
+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
+ "EventCode": "0xc1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x400000",
- "Unit": "CHA"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just NotNearMem",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x800000",
- "Unit": "CHA"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just NonCoherent",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x1000000",
- "Unit": "CHA"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy : Just ISOC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x2000000",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x01",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x01",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x02",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x10",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x10",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x20",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x20",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x80",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x80",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x02",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x08",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : Messages",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
"UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x01",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x01",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x10",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x10",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x20",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x20",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x80",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x80",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
- "UMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
- "UMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x02",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x02",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x04",
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x04",
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x08",
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x08",
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x10",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x10",
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
"UMask": "0x40",
"Unit": "IIO"
},
{
"BriefDescription": "Number Transactions requested of the CPU : Messages",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x100",
- "UMask": "0x80",
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
"EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x200",
- "UMask": "0x80",
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
- "PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
- "PerPkg": "1",
- "UMaskExt": "0x0C",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Full : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
+ "BriefDescription": "Number Transactions requested of the CPU : Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Prefetch CAM Deallocs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6E",
- "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6F",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI",
+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PortMask": "0x100",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PortMask": "0x200",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PortMask": "0x01",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PortMask": "0x02",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PortMask": "0x04",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PortMask": "0x08",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PortMask": "0x10",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PortMask": "0x20",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PortMask": "0x40",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PortMask": "0x80",
+ "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH",
+ "BriefDescription": "Total Write Cache Occupancy : Any Source",
+ "EventCode": "0x0F",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.",
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
+ "BriefDescription": "Total Write Cache Occupancy : Snoops",
+ "EventCode": "0x0F",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
+ "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
+ "EventCode": "0x0f",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.",
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
+ "BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
+ "EventCode": "0x01",
+ "EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
+ "BriefDescription": "Coherent Ops : CLFlush",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
+ "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
+ "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
+ "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
+ "BriefDescription": "Coherent Ops : WbMtoI",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
+ "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP",
"UMask": "0x40",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
+ "BriefDescription": "FAF RF full",
+ "EventCode": "0x17",
+ "EventName": "UNC_I_FAF_FULL",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
+ "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+ "EventCode": "0x18",
+ "EventName": "UNC_I_FAF_INSERTS",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x71",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH",
+ "BriefDescription": "Occupancy of the IRP FAF queue.",
+ "EventCode": "0x19",
+ "EventName": "UNC_I_FAF_OCCUPANCY",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP",
+ "BriefDescription": "FAF allocation -- sent to ADQ",
+ "EventCode": "0x16",
+ "EventName": "UNC_I_FAF_TRANSACTIONS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION",
+ "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.EVICTS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT",
+ "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B",
+ "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
+ "EventCode": "0x20",
+ "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC",
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD",
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
+ "EventCode": "0x1e",
+ "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL",
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
+ "EventCode": "0x1e",
+ "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY",
+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY",
+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+ "EventCode": "0x1e",
+ "EventName": "UNC_I_MISC0.FAST_REQ",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH",
+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers >From Primary to Secondary",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH",
+ "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints >From Primary to Secondary",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
+ "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI",
+ "BriefDescription": "Misc Events - Set 1 : Lost Forward",
+ "EventCode": "0x1F",
+ "EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
+ "BriefDescription": "Misc Events - Set 1 : Received Invalid",
+ "EventCode": "0x1F",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI",
+ "BriefDescription": "Misc Events - Set 1 : Received Valid",
+ "EventCode": "0x1F",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
+ "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
+ "EventCode": "0x1f",
+ "EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2",
+ "BriefDescription": "P2P Requests",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_P2P_INSERTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "P2P Requests : P2P requests from the ITC",
+ "Unit": "IRP"
},
{
- "BriefDescription": ": Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
+ "BriefDescription": "P2P Occupancy",
+ "EventCode": "0x15",
+ "EventName": "UNC_I_P2P_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy",
+ "Unit": "IRP"
},
{
- "BriefDescription": ": Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
+ "BriefDescription": "P2P Transactions : P2P completions",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": ": Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2",
+ "BriefDescription": "P2P Transactions : match if local only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "BriefDescription": "P2P Transactions : match if local and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "IRP"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "BriefDescription": "P2P Transactions : P2P Message",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "BriefDescription": "P2P Transactions : P2P reads",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
+ "BriefDescription": "P2P Transactions : Match if remote only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
+ "BriefDescription": "P2P Transactions : match if remote and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
"PerPkg": "1",
"UMask": "0x20",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Write Tracker Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Write Tracker Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
+ "BriefDescription": "P2P Transactions : P2P Writes",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
+ "UMask": "0x7e",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
+ "UMask": "0x74",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
+ "UMask": "0x72",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
+ "UMask": "0x78",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
+ "UMask": "0x71",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "BriefDescription": "Snoop Responses : Hit E or S",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "UMask": "0x4",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "BriefDescription": "Snoop Responses : Hit I",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "BriefDescription": "Snoop Responses : Hit M",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
+ "BriefDescription": "Snoop Responses : Miss",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "UMask": "0x1",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "BriefDescription": "Snoop Responses : SnpCode",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "BriefDescription": "Snoop Responses : SnpData",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x47",
- "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "BriefDescription": "Snoop Responses : SnpInv",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "UMask": "0x40",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
+ "BriefDescription": "Inbound Transaction Count : Atomic",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions",
+ "UMask": "0x10",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
+ "BriefDescription": "Inbound Transaction Count : Other",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.",
+ "UMask": "0x20",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
+ "BriefDescription": "Inbound Transaction Count : Writes",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+ "UMask": "0x2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
+ "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+ "UMask": "0x8",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
+ "BriefDescription": "AK Egress Allocations",
+ "EventCode": "0x0B",
+ "EventName": "UNC_I_TxC_AK_INSERTS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
+ "BriefDescription": "BL DRS Egress Cycles Full",
+ "EventCode": "0x05",
+ "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
+ "BriefDescription": "BL DRS Egress Inserts",
+ "EventCode": "0x02",
+ "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x19",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
+ "BriefDescription": "BL DRS Egress Occupancy",
+ "EventCode": "0x08",
+ "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
+ "BriefDescription": "BL NCB Egress Cycles Full",
+ "EventCode": "0x06",
+ "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
+ "BriefDescription": "BL NCB Egress Inserts",
+ "EventCode": "0x03",
+ "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
+ "BriefDescription": "BL NCB Egress Occupancy",
+ "EventCode": "0x09",
+ "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1a",
- "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
+ "BriefDescription": "BL NCS Egress Cycles Full",
+ "EventCode": "0x07",
+ "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
+ "BriefDescription": "BL NCS Egress Inserts",
+ "EventCode": "0x04",
+ "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
+ "BriefDescription": "BL NCS Egress Occupancy",
+ "EventCode": "0x0A",
+ "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x17",
- "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
+ "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "BriefDescription": "No AD0 Egress Credits Stalls",
+ "EventCode": "0x1A",
+ "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "BriefDescription": "No AD1 Egress Credits Stalls",
+ "EventCode": "0x1B",
+ "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "BriefDescription": "No BL Egress Credit Stalls",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0x0D",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0x0E",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
+ "BriefDescription": "Outbound Request Queue Occupancy",
+ "EventCode": "0x0C",
+ "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "Outbound Request Queue Occupancy : Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+ "Unit": "IRP"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4a",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "M2PCIe"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4b",
- "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : Local NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : Local NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : Remote NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : Remote NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Credit Occupancy : All",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : Local NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : Local NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : Remote NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : Remote NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Dedicated Credits Received : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : Local NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : Local NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : Remote NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : Remote NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Shared Credits Received : All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8B",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8B",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8B",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x48",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x49",
- "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x1b",
- "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x18",
- "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x8D",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x8D",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x8D",
+ "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4c",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4d",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4d",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4d",
- "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x2d",
- "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+ "BriefDescription": "M2M to iMC Bypass : Not Taken",
+ "EventCode": "0x22",
+ "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+ "BriefDescription": "M2M to iMC Bypass : Taken",
+ "EventCode": "0x22",
+ "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+ "BriefDescription": "M2M to iMC Bypass : Not Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UBOX"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+ "BriefDescription": "M2M to iMC Bypass : Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UBOX"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+ "BriefDescription": "Clockticks of the mesh to memory (M2M)",
+ "EventName": "UNC_M2M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M2M_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+ "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4D",
- "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+ "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "EventCode": "0x60",
+ "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+ "BriefDescription": "Number of reads in which direct to core transaction was overridden",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+ "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+ "EventCode": "0x28",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+ "BriefDescription": "Cycles when Direct2UPI was Disabled",
+ "EventCode": "0x27",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+ "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+ "EventCode": "0x29",
+ "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UBOX"
+ "PublicDescription": "Clockticks of the mesh to PCI (M2P)",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "BriefDescription": "Directory Hit : On NonDirty Line in A State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UBOX"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+ "BriefDescription": "Directory Hit : On NonDirty Line in I State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UBOX"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+ "BriefDescription": "Directory Hit : On NonDirty Line in L State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
"PerPkg": "1",
"UMask": "0x40",
- "Unit": "UBOX"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4E",
- "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+ "BriefDescription": "Directory Hit : On NonDirty Line in S State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UBOX"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+ "BriefDescription": "Directory Hit : On Dirty Line in A State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UBOX"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+ "BriefDescription": "Directory Hit : On Dirty Line in I State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UBOX"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Directory Hit : On Dirty Line in L State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Directory Hit : On Dirty Line in S State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Directory Miss : On NonDirty Line in A State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Directory Miss : On NonDirty Line in I State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Directory Miss : On NonDirty Line in L State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Directory Miss : On NonDirty Line in S State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Directory Miss : On Dirty Line in A State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Directory Miss : On Dirty Line in I State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Directory Miss : On Dirty Line in L State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Directory Miss : On Dirty Line in S State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.",
+ "EventCode": "0x2e",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Distress signal asserted : DPT Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Distress signal asserted : DPT Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Distress signal asserted : PMM Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Distress signal asserted : PMM Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "UNC_M2M_DISTRESS_PMM",
+ "EventCode": "0xF2",
+ "EventName": "UNC_M2M_DISTRESS_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE",
+ "EventCode": "0xF1",
+ "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "EventCode": "0xBA",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xBA",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xBB",
+ "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xB7",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Horizontal IV Ring in Use : Left",
+ "EventCode": "0xB9",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Horizontal IV Ring in Use : Right",
+ "EventCode": "0xB9",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x704",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x104",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x140",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x102",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x101",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x110",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x108",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
+ "UMask": "0x120",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x204",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x240",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x202",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x201",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x210",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x208",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
+ "UMask": "0x220",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x440",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x740",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ISOCH",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x702",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.NORMAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x701",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x710",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x708",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.TO_PMM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x720",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1c10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x410",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x401",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x404",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_NI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x402",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x408",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x440",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x420",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
+ "UMask": "0x480",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x810",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x801",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x804",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_NI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x802",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x808",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x840",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x820",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
+ "UMask": "0x880",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL",
+ "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x1c01",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x1c04",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.NI",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1c02",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1c08",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1c40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1c20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x1c80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Write Tracker Inserts",
+ "EventCode": "0x64",
+ "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "BriefDescription": "Write Tracker Occupancy",
+ "EventCode": "0x65",
+ "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "EventCode": "0xE6",
+ "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "EventCode": "0xE6",
+ "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Number Packet Header Matches : MC Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Number Packet Header Matches : Mesh Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MESH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "EventCode": "0x73",
+ "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Prefetch CAM Cycles Full : Channel 2",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0",
+ "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2",
+ "EventCode": "0x6C",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "Prefetch CAM Deallocs",
+ "EventCode": "0x6E",
+ "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2",
+ "EventCode": "0x6F",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
+ "EventCode": "0x6f",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2a",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
+ "EventCode": "0x6f",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x15",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
"PerPkg": "1",
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
+ "EventCode": "0x74",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels",
+ "UMask": "0x15",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AK",
+ "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
+ "EventCode": "0x75",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x15",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.IV",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
"PerPkg": "1",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AK",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IV",
+ "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
+ "EventCode": "0x70",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AK",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.IV",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
+ "EventCode": "0x71",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AK",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.IV",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY",
"PerPkg": "1",
"UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL",
+ "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
+ "EventCode": "0x72",
+ "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL",
+ "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
+ "EventCode": "0x6d",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x2a",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
+ "EventCode": "0x6D",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x15",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "BriefDescription": "Prefetch CAM Occupancy : All Channels",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "Prefetch CAM Occupancy : Channel 1",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "Prefetch CAM Occupancy : Channel 2",
+ "EventCode": "0x6A",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": ": All Channels",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x7",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": ": Channel 0",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": ": Channel 1",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "BriefDescription": ": Channel 2",
+ "EventCode": "0x76",
+ "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+ "EventCode": "0x79",
+ "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
+ "EventCode": "0x7A",
+ "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
+ "EventCode": "0x78",
+ "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+ "EventCode": "0x77",
+ "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_M2M_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD",
+ "BriefDescription": "AD Ingress (from CMS) Full",
+ "EventCode": "0x04",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK",
+ "BriefDescription": "AD Ingress (from CMS) Not Empty",
+ "EventCode": "0x03",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD",
+ "BriefDescription": "AD Ingress (from CMS) Allocations",
+ "EventCode": "0x01",
+ "EventName": "UNC_M2M_RxC_AD_INSERTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV",
+ "BriefDescription": "AD Ingress (from CMS) Occupancy",
+ "EventCode": "0x02",
+ "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
+ "EventCode": "0x77",
+ "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M2M_RxC_AK_WR_CMP",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "BriefDescription": "BL Ingress (from CMS) Full",
+ "EventCode": "0x08",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "BL Ingress (from CMS) Not Empty",
+ "EventCode": "0x07",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "BL Ingress (from CMS) Allocations",
+ "EventCode": "0x05",
+ "EventName": "UNC_M2M_RxC_BL_INSERTS",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "BriefDescription": "BL Ingress (from CMS) Occupancy",
+ "EventCode": "0x06",
+ "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL",
- "PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "BriefDescription": "Transgress Ingress Bypass : AK",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M2M_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : AK",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL",
+ "BriefDescription": "Transgress Injection Starvation : IV",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD",
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AK",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.IV",
+ "BriefDescription": "Transgress Ingress Allocations : AK",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M2M_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV",
+ "BriefDescription": "Transgress Ingress Occupancy : AK",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CHA"
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD",
+ "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK",
+ "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD",
+ "BriefDescription": "Retry - Mem Mirroring Mode",
+ "EventCode": "0x35",
+ "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV",
+ "BriefDescription": "Retry - Mem Mirroring Mode",
+ "EventCode": "0x36",
+ "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD",
+ "BriefDescription": "Scoreboard Accepts",
+ "EventCode": "0x2F",
+ "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL",
+ "BriefDescription": "Scoreboard Rejects",
+ "EventCode": "0x30",
+ "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL",
+ "BriefDescription": "Scoreboard Accepts",
+ "EventCode": "0x31",
+ "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "Scoreboard Rejects",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1",
+ "BriefDescription": "Tag Hit : Clean NearMem Read Hit",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs).",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1",
+ "BriefDescription": "Tag Hit : Dirty NearMem Read Hit",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs).",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1",
+ "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0",
+ "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1",
+ "BriefDescription": "Tag Miss",
+ "EventCode": "0x61",
+ "EventName": "UNC_M2M_TAG_MISS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "BriefDescription": "Number AD Ingress Credits",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2M_TGR_AD_CREDITS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "BriefDescription": "Number BL Ingress Credits",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2M_TGR_BL_CREDITS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "BriefDescription": "Tracker Cycles Full : Channel 0",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_FULL.CH0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "BriefDescription": "Tracker Cycles Full : Channel 1",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "BriefDescription": "Tracker Cycles Full : Channel 2",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_FULL.CH2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "BriefDescription": "Tracker Inserts : Channel 0",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "BriefDescription": "Tracker Inserts : Channel 1",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "BriefDescription": "Tracker Inserts : Channel 2",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "BriefDescription": "Tracker Cycles Not Empty : Channel 0",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_NE.CH0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0",
+ "BriefDescription": "Tracker Cycles Not Empty : Channel 1",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_NE.CH1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0",
+ "BriefDescription": "Tracker Cycles Not Empty : Channel 2",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_NE.CH2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0",
+ "BriefDescription": "Tracker Occupancy : Channel 0",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0",
+ "BriefDescription": "Tracker Occupancy : Channel 1",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1",
+ "BriefDescription": "Tracker Occupancy : Channel 2",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1",
+ "BriefDescription": "AD Egress (to CMS) Credit Acquired",
+ "EventCode": "0x0d",
+ "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1",
+ "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+ "EventCode": "0x0e",
+ "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0",
+ "BriefDescription": "AD Egress (to CMS) Full",
+ "EventCode": "0x0c",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1",
+ "BriefDescription": "AD Egress (to CMS) Not Empty",
+ "EventCode": "0x0b",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC",
+ "BriefDescription": "AD Egress (to CMS) Allocations",
+ "EventCode": "0x09",
+ "EventName": "UNC_M2M_TxC_AD_INSERTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+ "EventCode": "0x0f",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "AD Egress (to CMS) Occupancy",
+ "EventCode": "0x0A",
+ "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.NDR",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "AKC Credits",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M2M_TxC_AKC_CREDITS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD",
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Full : All",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x3",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x88",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0xa0",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "AK Egress (to CMS) Full",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x90",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "AK Egress (to CMS) Not Empty : All",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x3",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD",
+ "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "BriefDescription": "AK Egress (to CMS) Not Empty",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD",
+ "BriefDescription": "AK Egress (to CMS) Not Empty",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "AK Egress (to CMS) Not Empty",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "AK Egress (to CMS) Allocations : All",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "AK Egress (to CMS) Allocations",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "AK Egress (to CMS) Occupancy : All",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "AK Egress (to CMS) Occupancy",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "AK Egress (to CMS) Occupancy",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "AK Egress (to CMS) Occupancy",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "BL Egress (to CMS) Full : All",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "BL Egress (to CMS) Not Empty : All",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "BL Egress (to CMS) Allocations : All",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x3",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2M"
},
- {
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ {
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8B",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8D",
- "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2M"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB6",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBB",
- "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB7",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB8",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB9",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE6",
- "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAC",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x08",
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"Unit": "M2M"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAA",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AK",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.IV",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AK",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.IV",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "Vertical IV Ring in Use : Down",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "WPQ Flush : Channel 0",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_WPQ_FLUSH.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "WPQ Flush : Channel 1",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_WPQ_FLUSH.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "WPQ Flush : Channel 2",
+ "EventCode": "0x58",
+ "EventName": "UNC_M2M_WPQ_FLUSH.CH2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0",
+ "EventCode": "0x51",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1",
+ "EventCode": "0x51",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2",
+ "EventCode": "0x51",
+ "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "Write Tracker Cycles Full : Channel 0",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "Write Tracker Cycles Full : Channel 1",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "Write Tracker Cycles Full : Channel 2",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "Write Tracker Cycles Full : Mirror",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "Write Tracker Inserts : Channel 0",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "Write Tracker Inserts : Channel 1",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "Write Tracker Inserts : Channel 2",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.CH2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "Write Tracker Cycles Not Empty",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "Write Tracker Cycles Not Empty",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
+ "EventCode": "0x63",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
+ "EventCode": "0x63",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2",
+ "EventCode": "0x63",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
+ "EventCode": "0x62",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
+ "EventCode": "0x62",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2",
+ "EventCode": "0x62",
+ "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "Write Tracker Occupancy : Channel 0",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
+ "BriefDescription": "Write Tracker Occupancy : Channel 1",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "Write Tracker Occupancy : Channel 2",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
+ "BriefDescription": "Write Tracker Occupancy : Mirror",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
+ "BriefDescription": "Write Tracker Occupancy",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
+ "BriefDescription": "Write Tracker Occupancy",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
+ "BriefDescription": "Write Tracker Posted Inserts : Channel 0",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "Write Tracker Posted Inserts : Channel 1",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "Write Tracker Posted Inserts : Channel 2",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x2",
"Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "Write Tracker Posted Occupancy : Channel 2",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x4",
"Unit": "M2M"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x81",
+ "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x83",
+ "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x89",
+ "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8a",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8b",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8b",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8b",
+ "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x44",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
+ "EventCode": "0x85",
+ "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
+ "EventCode": "0x87",
+ "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
+ "EventCode": "0x8c",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
+ "EventCode": "0x8d",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
+ "EventCode": "0x8d",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
+ "EventCode": "0x8d",
+ "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
+ "EventCode": "0x8e",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8f",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
+ "EventCode": "0x8f",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
+ "EventCode": "0x8f",
+ "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "BriefDescription": "Clockticks of the mesh to PCI (M2P)",
+ "EventCode": "0x01",
+ "EventName": "UNC_M2P_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M2P_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "BriefDescription": "Distress signal asserted : DPT Local",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
+ "BriefDescription": "Distress signal asserted : DPT Remote",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
+ "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
+ "BriefDescription": "Distress signal asserted : PMM Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
+ "BriefDescription": "Distress signal asserted : PMM Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xaf",
+ "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
+ "EventCode": "0xba",
+ "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xba",
+ "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
+ "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
+ "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
+ "EventCode": "0xb6",
+ "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xbb",
+ "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
+ "EventCode": "0xb7",
+ "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
+ "EventCode": "0xb8",
+ "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "BriefDescription": "Horizontal IV Ring in Use : Left",
+ "EventCode": "0xb9",
+ "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "BriefDescription": "Horizontal IV Ring in Use : Right",
+ "EventCode": "0xb9",
+ "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : DRS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCB",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0",
"PerPkg": "1",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
+ "BriefDescription": "M2PCIe IIO Credit Acquired : NCS",
+ "EventCode": "0x33",
+ "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1",
"PerPkg": "1",
+ "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
"UMask": "0x20",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
+ "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
+ "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
+ "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS",
+ "EventCode": "0x34",
+ "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x1a",
+ "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Local P2P Shared Credits Returned : Agent0",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Local P2P Shared Credits Returned : Agent1",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x81",
- "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Local P2P Shared Credits Returned : Agent2",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x83",
- "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x89",
- "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS",
+ "EventCode": "0x4a",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8a",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS",
+ "EventCode": "0x4b",
+ "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8b",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
+ "EventCode": "0xe6",
+ "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8b",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
+ "EventCode": "0xe6",
+ "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8b",
- "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "P2P Credit Occupancy : All",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "P2P Credit Occupancy : Local NCB",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "P2P Credit Occupancy : Local NCS",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "P2P Credit Occupancy : Remote NCB",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "P2P Credit Occupancy : Remote NCS",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Dedicated Credits Received : All",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Dedicated Credits Received : Local NCB",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Dedicated Credits Received : Local NCS",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x84",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Dedicated Credits Received : Remote NCB",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Dedicated Credits Received : Remote NCS",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Shared Credits Received : All",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x85",
- "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Shared Credits Received : Local NCB",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Shared Credits Received : Local NCS",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Shared Credits Received : Remote NCB",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Shared Credits Received : Remote NCS",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0",
+ "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6",
+ "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS",
+ "EventCode": "0x1b",
+ "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8c",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7",
+ "BriefDescription": "Remote P2P Shared Credits Returned : Agent0",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8d",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "BriefDescription": "Remote P2P Shared Credits Returned : Agent1",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8d",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "BriefDescription": "Remote P2P Shared Credits Returned : Agent2",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8d",
- "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0",
+ "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1",
+ "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8e",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8f",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8f",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8f",
- "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaf",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS",
+ "EventCode": "0x4c",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xba",
- "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS",
+ "EventCode": "0x4d",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xba",
- "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB",
+ "EventCode": "0x4d",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS",
+ "EventCode": "0x4d",
+ "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
+ "EventCode": "0xac",
+ "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
+ "EventCode": "0xac",
+ "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb6",
- "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
+ "EventCode": "0xac",
+ "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
+ "EventCode": "0xac",
+ "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xbb",
- "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
+ "EventCode": "0xaa",
+ "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb7",
- "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
+ "EventCode": "0xad",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb8",
- "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Sink Starvation on Vertical Ring : AD",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb9",
- "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb9",
- "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe6",
- "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe6",
- "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
+ "EventCode": "0xab",
+ "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xac",
- "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_M2P_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xac",
- "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xac",
- "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xac",
- "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xaa",
- "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC",
+ "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xad",
- "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB",
"PerPkg": "1",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xe5",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xab",
- "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xe5",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe5",
"EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
"EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
"EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD",
+ "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xe2",
+ "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe5",
- "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xe2",
+ "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe2",
"EventName": "UNC_M2P_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.IV",
+ "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
"EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD",
+ "EventName": "UNC_M2P_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xe3",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe2",
- "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xe3",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe3",
"EventName": "UNC_M2P_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Injection Starvation : IV",
"EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe3",
- "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xe1",
+ "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AK",
+ "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AK",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.IV",
+ "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe1",
"EventName": "UNC_M2P_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD",
+ "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
"EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL",
+ "EventName": "UNC_M2P_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe1",
- "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xe0",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AK",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AK",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xe0",
"EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
"EventCode": "0xe0",
- "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL",
+ "EventName": "UNC_M2P_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd0",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd2",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd4",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xd6",
"EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xd6",
+ "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xd6",
+ "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd1",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd1",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd1",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd3",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd3",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd3",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd5",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd5",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd5",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xd7",
+ "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2P_TxC_CREDITS.PMM",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ",
+ "EventCode": "0x2d",
+ "EventName": "UNC_M2P_TxC_CREDITS.PRQ",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd6",
- "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0",
+ "PerPkg": "1",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd6",
- "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd1",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd1",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd1",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd3",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd3",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd3",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AD_0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AD_1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd5",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd7",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.BL_0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd7",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "Egress (to CMS) Ingress",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_TxC_INSERTS.BL_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xd7",
- "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xa6",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa6",
"EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
"EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xa7",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa6",
- "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xa7",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa7",
"EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
"EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xa2",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa7",
- "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xa2",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa2",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
"EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xa3",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa2",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xa3",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa3",
"EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
"EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xa1",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa3",
- "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xa1",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa1",
"EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
"EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xa4",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa1",
- "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xa4",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa4",
"EventName": "UNC_M2P_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
"EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xa0",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa4",
- "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xa0",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa0",
"EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
"EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa0",
- "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xa5",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xa5",
"EventName": "UNC_M2P_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
- "PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
"EventCode": "0xa5",
- "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL",
+ "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"EventCode": "0x9c",
- "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"EventCode": "0x9c",
- "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9c",
"EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9d",
"EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
"EventCode": "0x9d",
- "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9e",
"EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9e",
"EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x94",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
"EventCode": "0x94",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x95",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x95",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x96",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
"EventCode": "0x96",
- "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x97",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x97",
"EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x92",
"EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M2PCIe"
},
+ {
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x93",
"EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x93",
"EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x98",
"EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
"EventCode": "0x98",
- "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x99",
"EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x99",
"EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x90",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
"EventCode": "0x90",
- "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x91",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x91",
"EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9a",
"EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
"EventCode": "0x9a",
- "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1",
+ "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x9b",
"EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb0",
- "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb0",
- "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
- "PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb0",
"EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb4",
- "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xb0",
+ "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb4",
- "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xb0",
+ "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb4",
"EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb1",
- "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xb4",
+ "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb1",
- "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xb4",
+ "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb1",
"EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb2",
- "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xb1",
+ "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb2",
- "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xb1",
+ "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb2",
"EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xb3",
- "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xb2",
+ "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xb2",
+ "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xb3",
"EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xb3",
+ "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP",
+ "PerPkg": "1",
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
"EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
"EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
"EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M2PCIe"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
"EventCode": "0xb5",
- "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD",
+ "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M2PCIe"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
"EventCode": "0x81",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
"EventCode": "0x81",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
"EventCode": "0x81",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
"EventCode": "0x83",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
"EventCode": "0x83",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
"EventCode": "0x83",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
"EventCode": "0x89",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
"EventCode": "0x89",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
"EventCode": "0x89",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
"EventCode": "0x8B",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
"EventCode": "0x8B",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
"EventCode": "0x8B",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
"EventCode": "0x85",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
"EventCode": "0x85",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
"EventCode": "0x85",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
"EventCode": "0x87",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
"EventCode": "0x87",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
"EventCode": "0x87",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
"EventCode": "0x8D",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
"EventCode": "0x8D",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
"EventCode": "0x8D",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR6",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR7",
"PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
+ "EventCode": "0x8F",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "PerPkg": "1",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR8",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR9",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10",
+ "BriefDescription": "CBox AD Credits Empty : Requests",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : Vertical",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT",
+ "BriefDescription": "CBox AD Credits Empty : Snoops",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : Horizontal",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ",
+ "BriefDescription": "CBox AD Credits Empty : VNA Messages",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+ "PerPkg": "1",
+ "PublicDescription": "CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "CBox AD Credits Empty : Writebacks",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+ "PerPkg": "1",
+ "PublicDescription": "CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)",
+ "EventCode": "0x01",
+ "EventName": "UNC_M3UPI_CLOCKTICKS",
+ "PerPkg": "1",
+ "PublicDescription": "Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xc0",
+ "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "D2C Sent",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M3UPI_D2C_SENT",
+ "PerPkg": "1",
+ "PublicDescription": "D2C Sent : Count cases BL sends direct to core",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "D2U Sent",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M3UPI_D2U_SENT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_NONLOCAL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_IV",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xBA",
- "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "Distress signal asserted : Horizontal",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ",
+ "PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Distress signal asserted : PMM Local",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL",
+ "PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Distress signal asserted : PMM Remote",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "PerPkg": "1",
+ "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Distress signal asserted : Vertical",
+ "EventCode": "0xAF",
+ "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBA",
"EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Egress Blocking due to Ordering requirements : Up",
+ "EventCode": "0xBA",
+ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "PerPkg": "1",
+ "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal IV Ring in Use : Left",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB9",
"EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal IV Ring in Use : Right",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xB9",
"EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO2",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO3",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO4",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO5",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "M2 BL Credits Empty : IIO5",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE6",
"EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xE6",
"EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AD - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AD - Slot 1",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AD - Slot 2",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AK - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : AK - Slot 2",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Multi Slot Flit Received : BL - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+ "PerPkg": "1",
+ "PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.",
"EventCode": "0xAA",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
"EventCode": "0xAA",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
"EventCode": "0xAA",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
"EventCode": "0xAD",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : BL",
"EventCode": "0xAD",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Horizontal Ring : IV",
"EventCode": "0xAD",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : AD",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Vertical Ring",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC",
+ "PerPkg": "1",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xae",
+ "EventName": "UNC_M3UPI_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD",
+ "BriefDescription": "Lost Arb for VN0 : REQ on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD",
+ "BriefDescription": "Lost Arb for VN0 : RSP on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "Lost Arb for VN0 : SNP on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "Lost Arb for VN0 : NCB on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL",
+ "BriefDescription": "Lost Arb for VN0 : NCS on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE5",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL",
+ "BriefDescription": "Lost Arb for VN0 : RSP on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD",
+ "BriefDescription": "Lost Arb for VN0 : WB on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AK",
+ "BriefDescription": "Lost Arb for VN1 : REQ on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD",
+ "BriefDescription": "Lost Arb for VN1 : RSP on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.IV",
+ "BriefDescription": "Lost Arb for VN1 : SNP on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "Lost Arb for VN1 : NCB on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "Lost Arb for VN1 : NCS on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD",
+ "BriefDescription": "Lost Arb for VN1 : RSP on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL",
+ "BriefDescription": "Lost Arb for VN1 : WB on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL",
+ "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD",
+ "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK",
+ "BriefDescription": "Arb Miscellaneous : Max Parallel Win",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD",
+ "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV",
+ "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side)",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL",
+ "BriefDescription": "No Credits to Arb for VN0 : REQ on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL",
+ "BriefDescription": "No Credits to Arb for VN0 : RSP on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN0 : SNP on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AK",
+ "BriefDescription": "No Credits to Arb for VN0 : NCB on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN0 : NCS on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.IV",
+ "BriefDescription": "No Credits to Arb for VN0 : RSP on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "No Credits to Arb for VN0 : WB on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
- },
- {
- "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN1 : REQ on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL",
+ "BriefDescription": "No Credits to Arb for VN1 : RSP on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL",
+ "BriefDescription": "No Credits to Arb for VN1 : SNP on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN1 : NCB on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK",
+ "BriefDescription": "No Credits to Arb for VN1 : NCS on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "No Credits to Arb for VN1 : RSP on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV",
+ "BriefDescription": "No Credits to Arb for VN1 : WB on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Can't Arb for VN0 : REQ on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Can't Arb for VN0 : RSP on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "Can't Arb for VN0 : SNP on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL",
+ "BriefDescription": "Can't Arb for VN0 : NCB on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xE0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL",
+ "BriefDescription": "Can't Arb for VN0 : NCS on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "Can't Arb for VN0 : RSP on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "Can't Arb for VN0 : WB on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "Can't Arb for VN1 : REQ on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "Can't Arb for VN1 : RSP on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "Can't Arb for VN1 : SNP on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "Can't Arb for VN1 : NCB on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
+ "BriefDescription": "Can't Arb for VN1 : NCS on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
+ "BriefDescription": "Can't Arb for VN1 : RSP on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "Can't Arb for VN1 : WB on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
+ "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
+ "BriefDescription": "Miscellaneous Credit Events",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 1",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "Miscellaneous Credit Events",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 2",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "Miscellaneous Credit Events",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "Credit Occupancy : Credits Consumed",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "Credit Occupancy : D2K Credits",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
"PerPkg": "1",
+ "PublicDescription": "Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "Credit Occupancy : Packets in BGF FIFO",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
+ "BriefDescription": "Credit Occupancy : Packets in BGF Path",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+ "PerPkg": "1",
+ "PublicDescription": "Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Credit Occupancy",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
"PerPkg": "1",
+ "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "BriefDescription": "Credit Occupancy",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "Credit Occupancy : Transmit Credits",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "Credit Occupancy : VNA In Use",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD3",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
+ "BriefDescription": "Data Flit Not Sent : All",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
+ "BriefDescription": "Data Flit Not Sent : No BGF Credits",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
+ "BriefDescription": "Data Flit Not Sent : No TxQ Credits",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD7",
- "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
+ "BriefDescription": "Data Flit Not Sent : TSV High",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD",
+ "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD",
+ "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
"PerPkg": "1",
+ "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending completion fifo is full",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK",
+ "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": ": slot 2 request naturally serviced during hold-off period",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": ": slot 2 request forcibly serviced during service window",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": ": slot 2 request received from link layer while idle (with no slot 2 request active immediately prior)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": ": slot 2 request withdrawn during hold-off period or service window",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD",
+ "BriefDescription": "Slotting BL Message Into Header Flit : All",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV",
+ "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "Flit Gen - Header 1 : Accumulate",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
+ "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL",
+ "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL",
+ "BriefDescription": "Flit Gen - Header 1",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD",
+ "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK",
+ "BriefDescription": "Flit Gen - Header 1",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD",
+ "BriefDescription": "Flit Gen - Header 1",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV",
+ "BriefDescription": "Flit Gen - Header 2 : Parallel Ok",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT",
"PerPkg": "1",
+ "PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "Flit Gen - Header 2 : Parallel Message",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
+ "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL",
+ "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL",
+ "BriefDescription": "Sent Header Flit : One Message",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD",
+ "BriefDescription": "Sent Header Flit : One Message in non-VNA",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK",
+ "BriefDescription": "Sent Header Flit : Two Messages",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Sent Header Flit : Two Messages : Two messages in flit; VNA flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD",
+ "BriefDescription": "Sent Header Flit : Three Messages",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Sent Header Flit : Three Messages : Three messages in flit; VNA flit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV",
+ "BriefDescription": "Sent Header Flit : One Slot Taken",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "Sent Header Flit : Two Slots Taken",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "Sent Header Flit : All Slots Taken",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD",
+ "BriefDescription": "Header Not Sent : All",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL",
+ "BriefDescription": "Header Not Sent : No BGF Credits",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL",
+ "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD",
+ "BriefDescription": "Header Not Sent : No TxQ Credits",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK",
+ "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD",
+ "BriefDescription": "Header Not Sent : TSV High",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV",
+ "BriefDescription": "Header Not Sent : Cycle valid for Flit",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "Message Held : Can't Slot AD",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
"PerPkg": "1",
+ "PublicDescription": "Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "Message Held : Can't Slot BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD",
+ "BriefDescription": "Message Held : Parallel Attempt",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL",
+ "BriefDescription": "Message Held : Parallel Success",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in paralle",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL",
+ "BriefDescription": "Message Held : VN0",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.VN0",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD",
+ "BriefDescription": "Message Held : VN1",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_HELD.VN1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0",
+ "BriefDescription": "VN0 message can't slot into flit : REQ on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0",
+ "BriefDescription": "VN0 message can't slot into flit : RSP on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0",
+ "BriefDescription": "VN0 message can't slot into flit : SNP on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0",
+ "BriefDescription": "VN0 message can't slot into flit : NCB on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1",
+ "BriefDescription": "VN0 message can't slot into flit : NCS on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1",
+ "BriefDescription": "VN0 message can't slot into flit : RSP on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1",
+ "BriefDescription": "VN0 message can't slot into flit : WB on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : REQ on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1",
+ "BriefDescription": "VN1 message can't slot into flit : RSP on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : SNP on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : NCB on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : NCS on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0",
+ "BriefDescription": "VN1 message can't slot into flit : RSP on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1",
+ "BriefDescription": "VN1 message can't slot into flit : WB on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1",
+ "BriefDescription": "Remote VNA Credits : Any In Use",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
"PerPkg": "1",
+ "PublicDescription": "Remote VNA Credits : Any In Use : At least one remote vna credit is in use",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1",
+ "BriefDescription": "Remote VNA Credits : Corrected",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0",
+ "BriefDescription": "Remote VNA Credits : Level < 1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1",
+ "BriefDescription": "Remote VNA Credits : Level < 10",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0",
+ "BriefDescription": "Remote VNA Credits : Level < 4",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0",
+ "BriefDescription": "Remote VNA Credits : Level < 5",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": ": remote vna credit count was less than 5 and allocation to ad or bl messages was required",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": ": remote vna credit count was less than 10 and allocation to vn0 or vn1 was required",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
+ "PerPkg": "1",
+ "PublicDescription": ": on vn0, remote vna credits were allocated only to ad messages, not to bl",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": ": on vn0, remote vna credits were allocated only to bl messages, not to ad",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": ": remote vna credits were allocated only to vn0, not to vn1",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
"PerPkg": "1",
+ "PublicDescription": ": on vn1, remote vna credits were allocated only to ad messages, not to bl",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": ": on vn1, remote vna credits were allocated only to bl messages, not to ad",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1",
+ "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": ": remote vna credits were allocated only to vn1, not to vn0",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1",
+ "BriefDescription": "Transgress Ingress Bypass : AD - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1",
+ "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : AK",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : BL - All",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Credited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1",
+ "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1",
+ "BriefDescription": "Transgress Ingress Bypass : IV",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1",
+ "BriefDescription": "Transgress Injection Starvation : AD - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AD - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1",
+ "BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0",
+ "BriefDescription": "Transgress Injection Starvation : AK",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0",
+ "BriefDescription": "Transgress Injection Starvation : BL - All",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0",
+ "BriefDescription": "Transgress Injection Starvation : BL - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0",
+ "BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1",
+ "BriefDescription": "Transgress Injection Starvation : IFV - Credited",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1",
+ "BriefDescription": "Transgress Injection Starvation : IV",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1",
+ "BriefDescription": "Transgress Injection Starvation",
+ "EventCode": "0xe4",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0",
+ "BriefDescription": "Transgress Ingress Allocations : AD - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC",
+ "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "Transgress Ingress Allocations : AK",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "Transgress Ingress Allocations : BL - All",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Credited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN",
+ "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD",
+ "BriefDescription": "Transgress Ingress Allocations : IV",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x11",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy : AK",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - All",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
+ "UMask": "0x44",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy : IV",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Up",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical IV Ring in Use : Down",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xB5",
- "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_CHA_RING_SRC_THRTL",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"PerPkg": "1",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_CHA_RxR_CRD_STARVED_1",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "Unit": "CHA"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Counting disabled",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_IIO_NOTHING",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PWT occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_IIO_PWT_OCCUPANCY",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Symbol Times on Link",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x82",
- "EventName": "UNC_IIO_SYMBOL_TIMES",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "P2P Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x14",
- "EventName": "UNC_I_P2P_INSERTS",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "P2P Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x15",
- "EventName": "UNC_I_P2P_OCCUPANCY",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress Allocations",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0B",
- "EventName": "UNC_I_TxC_AK_INSERTS",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL DRS Egress Cycles Full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x05",
- "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL DRS Egress Inserts",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x02",
- "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL DRS Egress Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x08",
- "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCB Egress Cycles Full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x06",
- "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCB Egress Inserts",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCB Egress Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x09",
- "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCS Egress Cycles Full",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x07",
- "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCS Egress Inserts",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL NCS Egress Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0A",
- "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
+ "PerPkg": "1",
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1C",
- "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "No AD0 Egress Credits Stalls",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1A",
- "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "No AD1 Egress Credits Stalls",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1B",
- "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x1D",
- "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0D",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0E",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x0C",
- "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x60",
- "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Write Tracker Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x64",
- "EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Write Tracker Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x65",
- "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD1",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x73",
- "EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x79",
- "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x78",
- "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x77",
- "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_M2M_RING_SRC_THRTL",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x04",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x03",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5C",
- "EventName": "UNC_M2M_RxC_AK_WR_CMP",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x08",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
+ "EventCode": "0xD7",
+ "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "BL Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x07",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+ "BriefDescription": "Failed ARB for AD : VN0 REQ Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_M2M_RxR_CRD_STARVED_1",
+ "BriefDescription": "Failed ARB for AD : VN0 RSP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x33",
- "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
+ "BriefDescription": "Failed ARB for AD : VN0 SNP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
+ "BriefDescription": "Failed ARB for AD : VN0 WB Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Retry - Mem Mirroring Mode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS",
+ "BriefDescription": "Failed ARB for AD : VN1 REQ Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Retry - Mem Mirroring Mode",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS",
+ "BriefDescription": "Failed ARB for AD : VN1 RSP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Scoreboard Accepts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS",
+ "BriefDescription": "Failed ARB for AD : VN1 SNP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Scoreboard Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
+ "BriefDescription": "Failed ARB for AD : VN1 WB Messages",
"EventCode": "0x30",
- "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Scoreboard Accepts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x31",
- "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Scoreboard Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x32",
- "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number AD Ingress Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_M2M_TGR_AD_CREDITS",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number BL Ingress Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_M2M_TGR_BL_CREDITS",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Egress (to CMS) Credit Acquired",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0d",
- "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+ "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0e",
- "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+ "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0c",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+ "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AD Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0b",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+ "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0f",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+ "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+ "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "AKC Credits",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x5F",
- "EventName": "UNC_M2M_TxC_AKC_CREDITS",
+ "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_M2P_RING_SRC_THRTL",
+ "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_M2P_RxR_CRD_STARVED_1",
+ "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
"PerPkg": "1",
- "Unit": "M2PCIe"
+ "PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc0",
- "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+ "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "D2C Sent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2B",
- "EventName": "UNC_M3UPI_D2C_SENT",
+ "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "D2U Sent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2A",
- "EventName": "UNC_M3UPI_D2U_SENT",
+ "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xae",
- "EventName": "UNC_M3UPI_RING_SRC_THRTL",
+ "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xe4",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1",
+ "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AK Flow Q Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x2F",
- "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
+ "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AK Flow Q Occupancy",
- "CounterType": "PGMABLE",
- "EventCode": "0x1E",
- "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
+ "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "FlowQ Generated Prefetch",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+ "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "IDI Lock/SplitLock Cycles",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_U_LOCK_CYCLES",
+ "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
"PerPkg": "1",
- "Unit": "UBOX"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "RACU Request",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x46",
- "EventName": "UNC_U_RACU_REQUESTS",
+ "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
"PerPkg": "1",
- "Unit": "UBOX"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x16",
- "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x20",
- "EventName": "UNC_UPI_PHY_INIT_CYCLES",
+ "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "L1 Req Nack",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_UPI_POWER_L1_NACK",
+ "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "L1 Req (same as L1 Ack)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x22",
- "EventName": "UNC_UPI_POWER_L1_REQ",
+ "BriefDescription": "AK Flow Q Inserts",
+ "EventCode": "0x2F",
+ "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
+ "BriefDescription": "AK Flow Q Occupancy",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x24",
- "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
+ "BriefDescription": "Failed ARB for BL : VN0 NCB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "CRC Errors Detected",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0B",
- "EventName": "UNC_UPI_RxL_CRC_ERRORS",
+ "BriefDescription": "Failed ARB for BL : VN0 NCS Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "LLR Requests Sent",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x08",
- "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
+ "BriefDescription": "Failed ARB for BL : VN0 RSP Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Consumed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x39",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
+ "BriefDescription": "Failed ARB for BL : VN0 WB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Consumed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x3A",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
+ "BriefDescription": "Failed ARB for BL : VN1 NCS Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VNA Credit Consumed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
+ "BriefDescription": "Failed ARB for BL : VN1 NCB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x28",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "BriefDescription": "Failed ARB for BL : VN1 RSP Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x29",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "BriefDescription": "Failed ARB for BL : VN1 WB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x26",
- "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
+ "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Tx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_UPI_TxL_BYPASSED",
+ "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x40",
- "EventName": "UNC_UPI_TxL_INSERTS",
+ "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_UPI_TxL_OCCUPANCY",
+ "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x45",
- "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VNA Credits Pending Return - Occupancy",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x44",
- "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
+ "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ALL",
+ "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x1FFFFF",
- "UMaskExt": "0x1FFF",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
+ "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
"PerPkg": "1",
- "UMask": "0x1bc1ff",
- "UMaskExt": "0x1bc1",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate Requests",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV",
+ "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x1A44FF",
- "UMaskExt": "0x1A44",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
+ "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x1bd0ff",
- "UMaskExt": "0x1bd0",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
+ "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x0bdfff",
- "UMaskExt": "0x0bdf",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
+ "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
"PerPkg": "1",
- "UMask": "0x15dfff",
- "UMaskExt": "0x15df",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE",
+ "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x1A04FF",
- "UMaskExt": "0x1A04",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE",
+ "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x1A01FF",
- "UMaskExt": "0x1A01",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE",
+ "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x1A08FF",
- "UMaskExt": "0x1A08",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE",
+ "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
"PerPkg": "1",
- "UMask": "0x1a10ff",
- "UMaskExt": "0x1a10",
- "Unit": "CHA"
+ "PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x1C19FF",
- "UMaskExt": "0x1C19",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x1844FF",
- "UMaskExt": "0x1844",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x19C1FF",
- "UMaskExt": "0x19C1",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x19C8FF",
- "UMaskExt": "0x19C8",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x19d0ff",
- "UMaskExt": "0x19d0",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL",
+ "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x189dff",
- "UMaskExt": "0x189d",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
+ "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0xC827FD01",
- "UMaskExt": "0xC827FD",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
"PerPkg": "1",
- "UMask": "0xC8A7FD01",
- "UMaskExt": "0xC8A7FD",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL",
"PerPkg": "1",
- "UMask": "0xC827FE01",
- "UMaskExt": "0xC827FE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH",
"PerPkg": "1",
- "UMask": "0xC8A7FE01",
- "UMaskExt": "0xC8A7FE",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL",
"PerPkg": "1",
- "UMask": "0xC88FFD01",
- "UMaskExt": "0xC88FFD",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL",
"PerPkg": "1",
- "UMask": "0xC897FD01",
- "UMaskExt": "0xC897FD",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
+ "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH",
"PerPkg": "1",
- "UMask": "0xC827FD01",
- "UMaskExt": "0xC827FD",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
+ "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL",
"PerPkg": "1",
- "UMask": "0xC8A7FD01",
- "UMaskExt": "0xC8A7FD",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL",
"PerPkg": "1",
- "UMask": "0xC887FD01",
- "UMaskExt": "0xC887FD",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0xC88FFE01",
- "UMaskExt": "0xC88FFE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC897FE01",
- "UMaskExt": "0xC897FE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - All",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL",
"PerPkg": "1",
- "UMask": "0xC827FE01",
- "UMaskExt": "0xC827FE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC8A7FE01",
- "UMaskExt": "0xC8A7FE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
+ "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC887FE01",
- "UMaskExt": "0xC887FE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL",
"PerPkg": "1",
- "UMask": "0xC803FD04",
- "UMaskExt": "0xC803FD",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0xCC43FD04",
- "UMaskExt": "0xCC43FD",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
+ "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC803FD04",
- "UMaskExt": "0xC803FD",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
+ "BriefDescription": "CMS Horizontal Bypass Used : AK",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK",
"PerPkg": "1",
- "UMask": "0xC803FF04",
- "UMaskExt": "0xC803FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
+ "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xC817FF01",
- "UMaskExt": "0xC817FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - All",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL",
"PerPkg": "1",
- "UMask": "0xC827FF01",
- "UMaskExt": "0xC827FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC8A7FF01",
- "UMaskExt": "0xC8A7FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; CRd Pref from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
+ "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC88FFF01",
- "UMaskExt": "0xC88FFF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
+ "BriefDescription": "CMS Horizontal Bypass Used : IV",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0xC803FF04",
- "UMaskExt": "0xC803FF",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL",
"PerPkg": "1",
- "UMask": "0xCC43FF04",
- "UMaskExt": "0xCC43FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0xC887FF01",
- "UMaskExt": "0xC887FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xCCC7FF01",
- "UMaskExt": "0xCCC7FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK",
"PerPkg": "1",
- "UMask": "0xC827FF01",
- "UMaskExt": "0xC827FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8A7FF01",
- "UMaskExt": "0xC8A7FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; CRd Pref from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL",
"PerPkg": "1",
- "UMask": "0xC88FFF01",
- "UMaskExt": "0xC88FFF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC897FF01",
- "UMaskExt": "0xC897FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC896FE01",
- "UMaskExt": "0xC896FE",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0xC8977E01",
- "UMaskExt": "0xC8977E",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL",
"PerPkg": "1",
- "UMask": "0xC806FE01",
- "UMaskExt": "0xC806FE",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0xC8077E01",
- "UMaskExt": "0xC8077E",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC886FE01",
- "UMaskExt": "0xC886FE",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK",
"PerPkg": "1",
- "UMask": "0xC8877E01",
- "UMaskExt": "0xC8877E",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8D7FF01",
- "UMaskExt": "0xC8D7FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL",
"PerPkg": "1",
- "UMask": "0xCC47FF01",
- "UMaskExt": "0xCC47FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0xCC23FF04",
- "UMaskExt": "0xCC23FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8C3FF04",
- "UMaskExt": "0xC8C3FF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0xcc27ff01",
- "UMaskExt": "0xcc27ff",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL",
"PerPkg": "1",
- "UMask": "0xC8978A01",
- "UMaskExt": "0xC8978A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0xC8968A01",
- "UMaskExt": "0xC8968A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8970A01",
- "UMaskExt": "0xC8970A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0xc8678a01",
- "UMaskExt": "0xc8678a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xc8668a01",
- "UMaskExt": "0xc8668a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL",
"PerPkg": "1",
- "UMask": "0xc8670a01",
- "UMaskExt": "0xc8670a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC8678601",
- "UMaskExt": "0xC86786",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8668601",
- "UMaskExt": "0xC86686",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM",
+ "BriefDescription": "CMS Horizontal Egress Inserts : IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0xc86f8a01",
- "UMaskExt": "0xc86f8a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL",
"PerPkg": "1",
- "UMask": "0xc86e8a01",
- "UMaskExt": "0xc86e8a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0xc86f0a01",
- "UMaskExt": "0xc86f0a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xC86F8601",
- "UMaskExt": "0xC86F86",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AK",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK",
"PerPkg": "1",
- "UMask": "0xC86E8601",
- "UMaskExt": "0xC86E86",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8168A01",
- "UMaskExt": "0xC8168A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL",
"PerPkg": "1",
- "UMask": "0xC8170A01",
- "UMaskExt": "0xC8170A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0xC8978A01",
- "UMaskExt": "0xC8978A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xC8968A01",
- "UMaskExt": "0xC8968A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress NACKs : IV",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV",
"PerPkg": "1",
- "UMask": "0xC8970A01",
- "UMaskExt": "0xC8970A",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL",
"PerPkg": "1",
- "UMask": "0xc867fe01",
- "UMaskExt": "0xc867fe",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x11",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0xc8678a01",
- "UMaskExt": "0xc8678a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"PerPkg": "1",
- "UMask": "0xc8668a01",
- "UMaskExt": "0xc8668a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AK",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0xc8670a01",
- "UMaskExt": "0xc8670a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"PerPkg": "1",
- "UMask": "0xc86ffe01",
- "UMaskExt": "0xc86ffe",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
- {
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM",
+ {
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL",
"PerPkg": "1",
- "UMask": "0xc86f8a01",
- "UMaskExt": "0xc86f8a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
+ "UMask": "0x44",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0xc86e8a01",
- "UMaskExt": "0xc86e8a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"PerPkg": "1",
- "UMask": "0xc86f0a01",
- "UMaskExt": "0xc86f0a",
- "Unit": "CHA"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "1",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Occupancy : IV",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "2",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "3",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "4",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "5",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "6",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "7",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "8",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "9",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "13",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "12",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "11",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "10",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "15",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "14",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC",
- "Counter": "16",
- "CounterType": "FREERUN",
- "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN",
+ "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0xC86FFE01",
- "UMaskExt": "0xC86FFE",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB",
+ "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS",
+ "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x11",
- "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS",
+ "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x2D",
- "EventName": "UNC_M2P_TxC_CREDITS.PMM",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Full",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Egress (to CMS) Cycles Not Empty",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : RFO Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Transactions homed locally Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"PerPkg": "1",
- "UMaskExt": "0x800",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Transactions homed remotely Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0",
"PerPkg": "1",
- "UMaskExt": "0x1000",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Remote snoop request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1",
"PerPkg": "1",
- "UMaskExt": "0x400",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : All Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0",
"PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Data Read Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1",
"PerPkg": "1",
- "UMaskExt": "0x01",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Write Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Flush or Invalidate Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : CRd Request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0",
"PerPkg": "1",
- "UMaskExt": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Local request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0",
"PerPkg": "1",
- "UMaskExt": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1",
"PerPkg": "1",
- "UMaskExt": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Remote non-snoop request Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0",
"PerPkg": "1",
- "UMaskExt": "0x200",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : All Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x1fe001",
- "UMaskExt": "0x1fe0",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x1fc1ff",
- "UMaskExt": "0x1fc1",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : Data Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
+ "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x1bc101",
- "UMaskExt": "0x1bc1",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x841ff",
- "UMaskExt": "0x841",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
+ "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x842ff",
- "UMaskExt": "0x842",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL",
+ "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x888ff",
- "UMaskExt": "0x888",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x17c2ff",
- "UMaskExt": "0x17c2",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cache Lookups : All transactions from Remote Agents",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
+ "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x1e20ff",
- "UMaskExt": "0x1e20",
- "Unit": "CHA"
+ "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty : IIO5",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB",
+ "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_DISTRESS_PMM",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xF2",
- "EventName": "UNC_M2M_DISTRESS_PMM",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xF1",
- "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE",
+ "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ISOCH",
+ "BriefDescription": "CMS Vertical Egress NACKs : IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x0702",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.FROM_TGR",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x0740",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+ "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x1C04",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x1C08",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM",
+ "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x1C20",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x1C40",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
+ "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1",
"PerPkg": "1",
- "UMaskExt": "0x1D",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0",
"PerPkg": "1",
- "UMaskExt": "0x1C",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Cycles Full : All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6C",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x15",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6f",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
+ "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x2a",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Occupancy : All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6A",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x76",
- "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1",
"PerPkg": "1",
- "UMask": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0",
"PerPkg": "1",
- "UMask": "0x0120",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1",
"PerPkg": "1",
- "UMask": "0x0108",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0",
"PerPkg": "1",
- "UMask": "0x0110",
- "UMaskExt": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1",
"PerPkg": "1",
- "UMask": "0x0220",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0",
"PerPkg": "1",
- "UMask": "0x0208",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0",
"PerPkg": "1",
- "UMask": "0x0210",
- "UMaskExt": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1",
"PerPkg": "1",
- "UMask": "0x0708",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC",
"PerPkg": "1",
- "UMask": "0x0710",
- "UMaskExt": "0x07",
- "Unit": "M2M"
+ "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM",
+ "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x0480",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
+ "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x0420",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE",
+ "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x0440",
- "UMaskExt": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM",
+ "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x0880",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM",
+ "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x0820",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE",
+ "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x0840",
- "UMaskExt": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0",
+ "BriefDescription": "UPI0 AD Credits Empty : VNA",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1",
+ "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x4F",
- "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2",
+ "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0",
+ "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1",
+ "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x51",
- "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2",
+ "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x7A",
- "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
+ "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+ "PerPkg": "1",
+ "PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UPI0 BL Credits Empty : VNA",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL",
+ "BriefDescription": "FlowQ Generated Prefetch",
+ "EventCode": "0x29",
+ "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Distress signal asserted : PMM Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6d",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
+ "BriefDescription": "Vertical AD Ring In Use : Down and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x2a",
- "Unit": "M2M"
+ "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x6D",
- "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Even",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x15",
- "Unit": "M2M"
+ "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PWC Hit to a 4K page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS",
+ "BriefDescription": "Vertical AD Ring In Use : Up and Odd",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PWC Hit to a 2M page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PWC Hit to a 1G page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS",
+ "BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PWT Hit to a 256T page",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Even",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": PageWalk cache fill",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS",
+ "BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Global IOTLB invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Domain-selective IOTLB invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN",
+ "BriefDescription": "Vertical AK Ring In Use : Down and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Page-selective IOTLB invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Even",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Context cache global invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL",
+ "BriefDescription": "Vertical AK Ring In Use : Up and Odd",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Domain-selective Context cache invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Device-selective Context cache invalidation cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x43",
- "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE",
+ "BriefDescription": "Vertical BL Ring in Use : Down and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : MsgB",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Even",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical BL Ring in Use : Up and Odd",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Ubox",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical IV Ring in Use : Down",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical IV Ring in Use : Up",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Local P2P",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Even",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Num requests sent by PCIe - by target : Abort",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8E",
- "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
- "FCMask": "0x07",
+ "BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
+ "EventCode": "0xB5",
+ "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "ITC address map 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x8F",
- "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU",
+ "BriefDescription": "VN0 Credit Used : WB on BL",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Issuing to IOMMU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 Credit Used : NCB on BL",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Processing response from IOMMU",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 Credit Used : REQ on AD",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Request Ownership",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 Credit Used : RSP on AD",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+ "PerPkg": "1",
+ "PublicDescription": "VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "VN0 Credit Used : SNP on AD",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Issuing final read or write of line",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 Credit Used : RSP on BL",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Writing line",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : WB on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": ": Passing data to be written",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x88",
- "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : NCB on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Occupancy of outbound request queue : To device",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC5",
- "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : REQ on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : RSP on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : SNP on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN0 No Credits : RSP on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "VN1 Credit Used : WB on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+ "PerPkg": "1",
+ "PublicDescription": "VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x91",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : NCB on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Issuing to IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : REQ on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Processing response from IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : RSP on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : SNP on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 Credit Used : RSP on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : WB on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request complete : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x92",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : NCB on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
"PerPkg": "1",
- "PortMask": "0xFF",
+ "PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - pass complete : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : REQ on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : RSP on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - pass complete : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : SNP on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "PCIe Request - pass complete : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x90",
- "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "VN1 No Credits : RSP on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x82",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0xa0",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x81",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x90",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
+ "PerPkg": "1",
+ "UMask": "0x84",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
+ "PerPkg": "1",
+ "UMask": "0xc0",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x10",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x86",
- "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
"UMask": "0x20",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Request Ownership",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
+ "EventCode": "0x7E",
+ "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Writing line",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.WR",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Incoming arbitration requests granted : Passing data to be written",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x87",
- "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x20",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD0",
- "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD1",
- "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number requests sent to PCIe from main die : >From IRP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number requests sent to PCIe from main die : >From ITC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xc2",
- "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC",
- "FCMask": "0x07",
+ "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
+ "EventCode": "0x7D",
+ "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.ARB",
"PerPkg": "1",
- "UMask": "0xC867FF01",
- "UMaskExt": "0xC867FF",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message is making arbitration request",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
"PerPkg": "1",
- "UMask": "0xC86FFF01",
- "UMaskExt": "0xC86FFF",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message arrived in ingress pipeline",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS",
"PerPkg": "1",
- "UMask": "0xC87FDE01",
- "UMaskExt": "0xC87FDE",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message took bypass path",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED",
"PerPkg": "1",
- "UMask": "0xC80EFE01",
- "UMaskExt": "0xC80EFE",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message was slotted into flit (non bypass)",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
"PerPkg": "1",
- "UMask": "0xC80F7E01",
- "UMaskExt": "0xC80F7E",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message lost arbitration",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
"PerPkg": "1",
- "UMask": "0xC88EFE01",
- "UMaskExt": "0xC88EFE",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message was dropped because it became too old",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
+ "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
"PerPkg": "1",
- "UMask": "0xC88F7E01",
- "UMaskExt": "0xC88F7E",
- "Unit": "CHA"
+ "PublicDescription": ": xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
+ "BriefDescription": "Number of kfclks",
+ "EventCode": "0x01",
+ "EventName": "UNC_UPI_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0xCD47FF01",
- "UMaskExt": "0xCD47FF",
- "Unit": "CHA"
+ "PublicDescription": "Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the GT/s speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
+ "BriefDescription": "Direct packet attempts : D2C",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
"PerPkg": "1",
- "UMask": "0xCC47FD01",
- "UMaskExt": "0xCC47FD",
- "Unit": "CHA"
+ "PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
+ "BriefDescription": "Direct packet attempts : D2K",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
"PerPkg": "1",
- "UMask": "0xCC47FE01",
- "UMaskExt": "0xCC47FE",
- "Unit": "CHA"
+ "PublicDescription": "Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0xC877DE01",
- "UMaskExt": "0xC877DE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
"PerPkg": "1",
- "UMask": "0xCCCFFF01",
- "UMaskExt": "0xCCCFFF",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
"PerPkg": "1",
- "UMask": "0xCCCFFD01",
- "UMaskExt": "0xCCCFFD",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
"PerPkg": "1",
- "UMask": "0xCCD7FD01",
- "UMaskExt": "0xCCD7FD",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0xCCCFFE01",
- "UMaskExt": "0xCCCFFE",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
+ "BriefDescription": "Cycles in L1",
+ "EventCode": "0x21",
+ "EventName": "UNC_UPI_L1_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0xCCCFFD01",
- "UMaskExt": "0xCCCFFD",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
"PerPkg": "1",
- "UMask": "0xCCD7FD01",
- "UMaskExt": "0xCCD7FD",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
"PerPkg": "1",
- "UMask": "0xCCCFFE01",
- "UMaskExt": "0xCCCFFE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
"PerPkg": "1",
- "UMask": "0xCCD7FE01",
- "UMaskExt": "0xCCD7FE",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x65",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT",
+ "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "EventCode": "0x16",
+ "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x70",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.THROTTLE",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ",
+ "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
+ "EventCode": "0x20",
+ "EventName": "UNC_UPI_PHY_INIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ",
+ "BriefDescription": "L1 Req Nack",
+ "EventCode": "0x23",
+ "EventName": "UNC_UPI_POWER_L1_NACK",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x66",
- "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP",
+ "BriefDescription": "L1 Req (same as L1 Ack).",
+ "EventCode": "0x22",
+ "EventName": "UNC_UPI_POWER_L1_REQ",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PublicDescription": "L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x67",
- "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x67",
- "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH",
+ "BriefDescription": "Cycles in L0p",
+ "EventCode": "0x25",
+ "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Pipe Rejects",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI",
+ "BriefDescription": "Cycles in L0",
+ "EventCode": "0x24",
+ "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
"PerPkg": "1",
- "UMaskExt": "0x400",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : PMM Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : PMM Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Distress signal asserted : PMM Local",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Distress signal asserted : PMM Remote",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xAF",
- "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Request",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0xC8678A01",
- "UMaskExt": "0xC8678A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
- "UMask": "0xC8668A01",
- "UMaskExt": "0xC8668A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x108",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
- "UMask": "0xC8670A01",
- "UMaskExt": "0xC8670A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x1aa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
- "UMask": "0xC86F8A01",
- "UMaskExt": "0xC86F8A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x12a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "UMask": "0xC86E8A01",
- "UMaskExt": "0xC86E8A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
- "UMask": "0xC86F0A01",
- "UMaskExt": "0xC86F0A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10c",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "UMask": "0xC8678A01",
- "UMaskExt": "0xC8678A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
- "UMask": "0xC8668A01",
- "UMaskExt": "0xC8668A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
- "UMask": "0xC8670A01",
- "UMaskExt": "0xC8670A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
- "UMask": "0xC86F8A01",
- "UMaskExt": "0xC86F8A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x109",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0xC86E8A01",
- "UMaskExt": "0xC86E8A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
+ "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
+ "EventCode": "0x05",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
- "UMask": "0xC86F0A01",
- "UMaskExt": "0xC86F0A",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10d",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DDR4 Access",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.DDR",
+ "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DDR4 Access",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR",
+ "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
+ "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
"PerPkg": "1",
- "UMask": "0xC8978601",
- "UMaskExt": "0xC89786",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "BriefDescription": "CRC Errors Detected",
+ "EventCode": "0x0B",
+ "EventName": "UNC_UPI_RxL_CRC_ERRORS",
"PerPkg": "1",
- "UMask": "0xC8968601",
- "UMaskExt": "0xC89686",
- "Unit": "CHA"
+ "PublicDescription": "CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "BriefDescription": "LLR Requests Sent",
+ "EventCode": "0x08",
+ "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
"PerPkg": "1",
- "UMask": "0xC8970601",
- "UMaskExt": "0xC89706",
- "Unit": "CHA"
+ "PublicDescription": "LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
+ "BriefDescription": "VN0 Credit Consumed",
+ "EventCode": "0x39",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
"PerPkg": "1",
- "UMask": "0xC8678601",
- "UMaskExt": "0xC86786",
- "Unit": "CHA"
+ "PublicDescription": "VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
+ "BriefDescription": "VN1 Credit Consumed",
+ "EventCode": "0x3A",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
"PerPkg": "1",
- "UMask": "0xC8668601",
- "UMaskExt": "0xC86686",
- "Unit": "CHA"
+ "PublicDescription": "VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
+ "BriefDescription": "VNA Credit Consumed",
+ "EventCode": "0x38",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
"PerPkg": "1",
- "UMask": "0xC8670601",
- "UMaskExt": "0xC86706",
- "Unit": "CHA"
+ "PublicDescription": "VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
+ "BriefDescription": "Valid Flits Received : All Data",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0xC86F8601",
- "UMaskExt": "0xC86F86",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
+ "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0xC86E8601",
- "UMaskExt": "0xC86E86",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
+ "BriefDescription": "Valid Flits Received : Data",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0xC86F0601",
- "UMaskExt": "0xC86F06",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
+ "BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0xC8168601",
- "UMaskExt": "0xC81686",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
+ "BriefDescription": "Valid Flits Received : LLCRD Not Empty",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
"PerPkg": "1",
- "UMask": "0xC8170601",
- "UMaskExt": "0xC81706",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
+ "BriefDescription": "Valid Flits Received : LLCTRL",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0xC8978601",
- "UMaskExt": "0xC89786",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
+ "BriefDescription": "Valid Flits Received : All Non Data",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0xC8968601",
- "UMaskExt": "0xC89686",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
+ "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0xC8970601",
- "UMaskExt": "0xC89706",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
+ "BriefDescription": "Valid Flits Received : Protocol Header",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0xC8678601",
- "UMaskExt": "0xC86786",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
+ "BriefDescription": "Valid Flits Received : Slot 0",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0xC8668601",
- "UMaskExt": "0xC86686",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
+ "BriefDescription": "Valid Flits Received : Slot 1",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMask": "0xC8670601",
- "UMaskExt": "0xC86706",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
+ "BriefDescription": "Valid Flits Received : Slot 2",
+ "EventCode": "0x03",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
"PerPkg": "1",
- "UMask": "0xC86F8601",
- "UMaskExt": "0xC86F86",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
"PerPkg": "1",
- "UMask": "0xC86E8601",
- "UMaskExt": "0xC86E86",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
"PerPkg": "1",
- "UMask": "0xC86F0601",
- "UMaskExt": "0xC86F06",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
"PerPkg": "1",
- "UMask": "0xC8F3FD04",
- "UMaskExt": "0xC8F3FD",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
"PerPkg": "1",
- "UMask": "0xCCD7FF01",
- "UMaskExt": "0xCCD7FF",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
"PerPkg": "1",
- "UMask": "0xC867FE01",
- "UMaskExt": "0xC867FE",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
"PerPkg": "1",
- "UMask": "0xC867FE01",
- "UMaskExt": "0xC867FE",
- "Unit": "CHA"
+ "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
"PerPkg": "1",
- "UMask": "0xC86FFE01",
- "UMaskExt": "0xC86FFE",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
"PerPkg": "1",
- "UMask": "0xC80EFE01",
- "UMaskExt": "0xC80EFE",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
"PerPkg": "1",
- "UMask": "0xC80F7E01",
- "UMaskExt": "0xC80F7E",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
"PerPkg": "1",
- "UMask": "0xC88EFE01",
- "UMaskExt": "0xC88EFE",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
"PerPkg": "1",
- "UMask": "0xC88F7E01",
- "UMaskExt": "0xC88F7E",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
"PerPkg": "1",
- "UMask": "0xC8C7FF01",
- "UMaskExt": "0xC8C7FF",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
"PerPkg": "1",
- "UMask": "0xC8D7FF01",
- "UMaskExt": "0xC8D7FF",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
"PerPkg": "1",
- "UMask": "0xCD47FF01",
- "UMaskExt": "0xCD47FF",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
"PerPkg": "1",
- "UMask": "0xCC57FF01",
- "UMaskExt": "0xCC57FF",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
"PerPkg": "1",
- "UMask": "0xCC27FF01",
- "UMaskExt": "0xCC27FF",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
"PerPkg": "1",
- "UMask": "0xCC47FF01",
- "UMaskExt": "0xCC47FF",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
"PerPkg": "1",
- "UMask": "0xCC47FD01",
- "UMaskExt": "0xCC47FD",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
"PerPkg": "1",
- "UMask": "0xCC47FE01",
- "UMaskExt": "0xCC47FE",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
"PerPkg": "1",
- "UMask": "0xC877DE01",
- "UMaskExt": "0xC877DE",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
+ "BriefDescription": "Cycles in L0p",
+ "EventCode": "0x27",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0xC87FDE01",
- "UMaskExt": "0xC87FDE",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "EventCode": "0x28",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
"PerPkg": "1",
- "UMask": "0xC867FF01",
- "UMaskExt": "0xC867FF",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "EventCode": "0x29",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
"PerPkg": "1",
- "UMask": "0xC86FFF01",
- "UMaskExt": "0xC86FFF",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
+ "BriefDescription": "Cycles in L0",
+ "EventCode": "0x26",
+ "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0xCCCFFF01",
- "UMaskExt": "0xCCCFFF",
- "Unit": "CHA"
+ "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0xCC23FF04",
- "UMaskExt": "0xCC23FF",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMask": "0xC8C3FF04",
- "UMaskExt": "0xC8C3FF",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0xCD43FF04",
- "UMaskExt": "0xCD43FF",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0xCD43FD04",
- "UMaskExt": "0xCD43FD",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Request",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0xCD43FE04",
- "UMaskExt": "0xCD43FE",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
- "UMask": "0xc8678601",
- "UMaskExt": "0xc86786",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x108",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
- "UMask": "0xc8668601",
- "UMaskExt": "0xc86686",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x1aa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiLF misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
- "UMask": "0xc8670601",
- "UMaskExt": "0xc86706",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x12a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "UMask": "0xc86f8601",
- "UMaskExt": "0xc86f86",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
- "UMask": "0xc86e8601",
- "UMaskExt": "0xc86e86",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10c",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts; WCiL misses from local IA",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "UMask": "0xc86f0601",
- "UMaskExt": "0xc86f06",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
- "UMask": "0xc8678601",
- "UMaskExt": "0xc86786",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
- "UMask": "0xc8668601",
- "UMaskExt": "0xc86686",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiLF misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
- "UMask": "0xc8670601",
- "UMaskExt": "0xc86706",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x109",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0xc86f8601",
- "UMaskExt": "0xc86f86",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR",
+ "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
+ "EventCode": "0x04",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
- "UMask": "0xc86e8601",
- "UMaskExt": "0xc86e86",
- "Unit": "CHA"
+ "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.",
+ "UMask": "0x10d",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy; WCiL misses from local IA",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR",
+ "BriefDescription": "Tx Flit Buffer Bypassed",
+ "EventCode": "0x41",
+ "EventName": "UNC_UPI_TxL_BYPASSED",
"PerPkg": "1",
- "UMask": "0xc86f0601",
- "UMaskExt": "0xc86f06",
- "Unit": "CHA"
+ "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
+ "BriefDescription": "Valid Flits Sent : All Data",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0xcc3fff01",
- "UMaskExt": "0xcc3fff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+ "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0x71",
- "Unit": "IRP"
+ "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+ "BriefDescription": "Valid Flits Sent : Data",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0x7e",
- "Unit": "IRP"
+ "PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+ "BriefDescription": "Valid Flits Sent : Idle",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0x74",
- "Unit": "IRP"
+ "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
- "Counter": "0,1",
- "CounterType": "PGMABLE",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+ "BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
"PerPkg": "1",
- "UMask": "0x72",
- "Unit": "IRP"
+ "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM",
+ "BriefDescription": "Valid Flits Sent : LLCTRL",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0xcc57fe01",
- "UMaskExt": "0xcc57fe",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM",
+ "BriefDescription": "Valid Flits Sent : All Non Data",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0xcc57fe01",
- "UMaskExt": "0xcc57fe",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
+ "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0xC837FE01",
- "UMaskExt": "0xC837FE",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
+ "BriefDescription": "Valid Flits Sent : Protocol Header",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0xC837FD01",
- "UMaskExt": "0xC837FD",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
+ "BriefDescription": "Valid Flits Sent : Slot 0",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0xC837FF01",
- "UMaskExt": "0xC837FF",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM",
+ "BriefDescription": "Valid Flits Sent : Slot 1",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMask": "0xcc57fd01",
- "UMaskExt": "0xcc57fd",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
+ "BriefDescription": "Valid Flits Sent : Slot 2",
+ "EventCode": "0x02",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
"PerPkg": "1",
- "UMask": "0xcc67ff01",
- "UMaskExt": "0xcc67ff",
- "Unit": "CHA"
+ "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
+ "BriefDescription": "Tx Flit Buffer Allocations",
+ "EventCode": "0x40",
+ "EventName": "UNC_UPI_TxL_INSERTS",
"PerPkg": "1",
- "UMask": "0xcc37ff01",
- "UMaskExt": "0xcc37ff",
- "Unit": "CHA"
+ "PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
+ "BriefDescription": "Tx Flit Buffer Occupancy",
+ "EventCode": "0x42",
+ "EventName": "UNC_UPI_TxL_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0xcc2fff01",
- "UMaskExt": "0xcc2fff",
- "Unit": "CHA"
+ "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
+ "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "EventCode": "0x45",
+ "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
"PerPkg": "1",
- "UMask": "0xC837FF01",
- "UMaskExt": "0xC837FF",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
+ "BriefDescription": "VNA Credits Pending Return - Occupancy",
+ "EventCode": "0x44",
+ "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0xC837FD01",
- "UMaskExt": "0xC837FD",
- "Unit": "CHA"
+ "PublicDescription": "VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
- "CounterType": "PGMABLE",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
+ "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+ "EventCode": "0xff",
+ "EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0xC837FE01",
- "UMaskExt": "0xC837FE",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x77",
- "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
+ "BriefDescription": "Message Received : Doorbell",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Code Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS",
+ "BriefDescription": "Message Received : Interrupt",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
"PerPkg": "1",
- "UMask": "0x1BD001",
- "UMaskExt": "0x1BD0",
- "Unit": "CHA"
+ "PublicDescription": "Message Received : Interrupt : Interrupts",
+ "UMask": "0x10",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : RFO Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS",
+ "BriefDescription": "Message Received : IPI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
"PerPkg": "1",
- "UMask": "0x1BC801",
- "UMaskExt": "0x1BC8",
- "Unit": "CHA"
+ "PublicDescription": "Message Received : IPI : Inter Processor Interrupts",
+ "UMask": "0x4",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ",
+ "BriefDescription": "Message Received : MSI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
"PerPkg": "1",
- "UMask": "0x1BD9FF",
- "UMaskExt": "0x1BD9",
- "Unit": "CHA"
+ "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS",
+ "BriefDescription": "Message Received : VLW",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
"PerPkg": "1",
- "UMask": "0x1BD901",
- "UMaskExt": "0x1BD9",
- "Unit": "CHA"
+ "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.",
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Locally HOMed Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM",
+ "BriefDescription": "IDI Lock/SplitLock Cycles",
+ "EventCode": "0x44",
+ "EventName": "UNC_U_LOCK_CYCLES",
"PerPkg": "1",
- "UMask": "0x0BD901",
- "UMaskExt": "0x0BD9",
- "Unit": "CHA"
+ "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
"PerPkg": "1",
- "UMask": "0x13D901",
- "UMaskExt": "0x13D9",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
"PerPkg": "1",
- "UMask": "0x09D9FF",
- "UMaskExt": "0x09D9",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
"PerPkg": "1",
- "UMask": "0x0A19FF",
- "UMaskExt": "0x0A19",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
"PerPkg": "1",
- "UMask": "0x11D9FF",
- "UMaskExt": "0x11D9",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT",
+ "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
"PerPkg": "1",
- "UMask": "0x1BD90E",
- "UMaskExt": "0x1BD9",
- "Unit": "CHA"
+ "UMask": "0x10",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
"PerPkg": "1",
- "UMask": "0x161901",
- "UMaskExt": "0x1619",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL",
- "FCMask": "0x04",
+ "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
"PerPkg": "1",
- "PortMask": "0xFF",
- "UMask": "0x03",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER",
+ "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
+ "EventCode": "0x4D",
+ "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
"PerPkg": "1",
- "UMask": "0x1A42FF",
- "UMaskExt": "0x1A42",
- "Unit": "CHA"
+ "UMask": "0x80",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Transactions homed locally",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
"PerPkg": "1",
- "UMask": "0x0BDFFF",
- "UMaskExt": "0x0BDF",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Transactions homed remotely",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM",
+ "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
"PerPkg": "1",
- "UMask": "0x15DFFF",
- "UMaskExt": "0x15DF",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
"PerPkg": "1",
- "UMask": "0x1A10FF",
- "UMaskExt": "0x1A10",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
"PerPkg": "1",
- "UMask": "0x19D0FF",
- "UMaskExt": "0x19D0",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
"PerPkg": "1",
- "UMask": "0x189DFF",
- "UMaskExt": "0x189D",
- "Unit": "CHA"
+ "UMask": "0x20",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Cache Lookups : Code Reads",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
"PerPkg": "1",
- "UMask": "0x1BD0FF",
- "UMaskExt": "0x1BD0",
- "Unit": "CHA"
+ "UMask": "0x40",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
- "Counter": "2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL",
- "FCMask": "0x04",
+ "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
"PerPkg": "1",
- "UMask": "0xFF",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
+ "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
+ "EventCode": "0x4F",
+ "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
"PerPkg": "1",
- "UMask": "0x15",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
+ "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
+ "EventCode": "0x4F",
+ "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
+ "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
+ "EventCode": "0x45",
+ "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.",
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x75",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
+ "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
+ "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDRAND",
"PerPkg": "1",
- "UMask": "0x15",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
+ "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDSEED",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x74",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
+ "BriefDescription": "RACU Request",
+ "EventCode": "0x46",
+ "EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker",
+ "Unit": "UBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
index 281f3605881d..ee4dac6fc797 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json
@@ -1,16 +1,13 @@
[
{
"BriefDescription": "Clockticks of the power control unit (PCU)",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -18,8 +15,6 @@
},
{
"BriefDescription": "UNC_P_DEMOTIONS",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS",
"PerPkg": "1",
@@ -27,44 +22,38 @@
},
{
"BriefDescription": "Phase Shed 0 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 1 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 2 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 3 Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
"Unit": "PCU"
},
{
"BriefDescription": "AVX256 Frequency Clipping",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x49",
"EventName": "UNC_P_FREQ_CLIP_AVX256",
"PerPkg": "1",
@@ -72,8 +61,6 @@
},
{
"BriefDescription": "AVX512 Frequency Clipping",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x4a",
"EventName": "UNC_P_FREQ_CLIP_AVX512",
"PerPkg": "1",
@@ -81,155 +68,137 @@
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x04",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x05",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C3 : Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
"EventCode": "0x06",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
- "BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x0A",
- "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+ "BriefDescription": "Number of cores in C-State : C0 and C1",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
+ "PublicDescription": "Number of cores in C-State : C0 and C1 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x09",
- "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+ "BriefDescription": "Number of cores in C-State : C3",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
+ "PublicDescription": "Number of cores in C-State : C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x72",
- "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+ "BriefDescription": "Number of cores in C-State : C6 and C7",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
+ "PublicDescription": "Number of cores in C-State : C6 and C7 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x42",
- "EventName": "UNC_P_VR_HOT_CYCLES",
+ "BriefDescription": "External Prochot",
+ "EventCode": "0x0A",
+ "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State : C0 and C1",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+ "BriefDescription": "Internal Prochot",
+ "EventCode": "0x09",
+ "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State : C3",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+ "BriefDescription": "Total Core C State Transition Cycles",
+ "EventCode": "0x72",
+ "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State : C6 and C7",
- "Counter": "0,1,2,3",
- "CounterType": "PGMABLE",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+ "BriefDescription": "VR Hot",
+ "EventCode": "0x42",
+ "EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
"Unit": "PCU"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
index d70864da5c67..e3227c7f2fe9 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json
@@ -1,269 +1,181 @@
[
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0xe"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003",
- "Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
"SampleAfterValue": "100007",
- "Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "STLB flush attempts",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
- "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
"SampleAfterValue": "100007",
- "Speculative": "1",
"UMask": "0x20"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 8949b58f89be..7e489749a0d4 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -12,7 +12,7 @@ GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-(3C|45|46),v32,haswell,core
GenuineIntel-6-3F,v26,haswellx,core
GenuineIntel-6-(7D|7E|A7),v1.15,icelake,core
-GenuineIntel-6-6[AC],v1.16,icelakex,core
+GenuineIntel-6-6[AC],v1.17,icelakex,core
GenuineIntel-6-3A,v22,ivybridge,core
GenuineIntel-6-3E,v22,ivytown,core
GenuineIntel-6-2D,v21,jaketown,core
--
2.39.0.314.g84b9a713c41-goog
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