lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Thu, 15 Dec 2022 17:13:07 +0100
From:   Michal Simek <michal.simek@....com>
To:     Kenneth Sloat <ksloat@...ignlinxhs.com>,
        "sean.anderson@...o.com" <sean.anderson@...o.com>,
        "michal.simek@...inx.com" <michal.simek@...inx.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [v2] pwm: xilinx: Fix u32 overflow issue in 32-bit width PWM
 mode.



On 12/15/22 17:07, Kenneth Sloat wrote:
> From: Ken Sloat <ksloat@...ignlinxhs.com>
> 
> This timer HW supports 8, 16 and 32-bit timer widths. This
> driver currently uses a u32 to store the max possible value
> of the timer. However, statements perform addition of 2 in
> xilinx_pwm_apply() when calculating the period_cycles and
> duty_cycles values. Since priv->max is a u32, this will
> result in an overflow to 1 which will not only be incorrect
> but fail on range comparison. This results in making it
> impossible to set the PWM in this timer mode.
> 
> There are two obvious solutions to the current problem:
> 1. Cast each instance where overflow occurs to u64.
> 2. Change priv->max from a u32 to a u64.
> 
> Solution #1 requires more code modifications, and leaves
> opportunity to introduce similar overflows if other math
> statements are added in the future. These may also go
> undetected if running in non 32-bit timer modes.
> 
> Solution #2 is the much smaller and cleaner approach and
> thus the chosen method in this patch.
> 
> This was tested on a Zynq UltraScale+ with multiple
> instances of the PWM IP.
> 
> Signed-off-by: Ken Sloat <ksloat@...ignlinxhs.com>
> ---
> Changes in v2:
>          -Update commit comments to explain specifically where this
>          problem occurs as well as compare solutions.
> 
> ---
>   include/clocksource/timer-xilinx.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/clocksource/timer-xilinx.h b/include/clocksource/timer-xilinx.h
> index c0f56fe6d22a..d116f18de899 100644
> --- a/include/clocksource/timer-xilinx.h
> +++ b/include/clocksource/timer-xilinx.h
> @@ -41,7 +41,7 @@ struct regmap;
>   struct xilinx_timer_priv {
>          struct regmap *map;
>          struct clk *clk;
> -       u32 max;
> +       u64 max;
>   };
> 
>   /**
> --
> 2.17.1

Reviewed-by: Michal Simek <michal.simek@....com>

Thanks,
Michal

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ