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Message-ID: <37dbef55-fd78-91db-33fb-ca1691fe1cc6@linaro.org>
Date:   Thu, 15 Dec 2022 11:56:12 -0800
From:   Richard Henderson <richard.henderson@...aro.org>
To:     Vineet Gupta <vineetg@...osinc.com>,
        Florian Weimer <fweimer@...hat.com>,
        Björn Töpel <bjorn@...nel.org>
Cc:     Darius Rad <darius@...espec.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Andrew Waterman <andrew@...ive.com>, stillson@...osinc.com,
        Paul Walmsley <paul.walmsley@...ive.com>, anup@...infault.org,
        atishp@...shpatra.org, guoren@...nel.org,
        Conor Dooley <conor.dooley@...rochip.com>,
        greentime.hu@...ive.com, vincent.chen@...ive.com,
        andy.chiu@...ive.com, arnd@...nel.org,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        libc-alpha@...rceware.org, christoph.muellner@...ll.eu,
        Aaron Durbin <adurbin@...osinc.com>, linux@...osinc.com
Subject: Re: RISCV Vector unit disabled by default for new task (was Re:
 [PATCH v12 17/17] riscv: prctl to enable vector commands)

On 12/15/22 10:57, Vineet Gupta wrote:
>> The other thing of note for SVE is that, with the default function ABI all of the SVE 
>> state is call-clobbered, which allows the kernel to drop instead of save state across 
>> system calls.  (There is a separate vector function call ABI when SVE types are used.)
> 
> For the RV psABI, it is similar - all V regs are caller-saved/call-clobbered [1] and 
> syscalls are not required to preserve V regs [2]
> However last I checked ARM documentation the ABI doc seemed to suggest that some (parts) 
> of the SVE regs are callee-saved [3]

As Pinski mentioned, just some low bits that overlap with scalar fp state; the high bits 
and the predicate registers gets zeroed when re-enabling.


>> So while strcpy may enable SVE for the thread, the next syscall may disable it again.
> 
> Next syscall could trash them, but will it disable SVE ?

Yes.  See fp_user_discard() in arch/arm64/kernel/syscall.c.


r~

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