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Date: Fri, 16 Dec 2022 16:37:14 +0200
From: Eugen Hristev <eugen.hristev@...rochip.com>
To: <linux-media@...r.kernel.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-phy@...ts.infradead.org>, <luis.oliveira@...opsys.com>,
Eugen Hristev <eugen.hristev@...rochip.com>,
Luis Oliveira <lolivei@...opsys.com>
Subject: [PATCH v5 1/4] dt-bindings: media: Document bindings for DW MIPI CSI-2 Host
Add bindings for Synopsys DesignWare MIPI CSI-2 host.
Signed-off-by: Luis Oliveira <lolivei@...opsys.com>
[eugen.hristev@...rochip.com: reworked binding, converted to yaml]
Signed-off-by: Eugen Hristev <eugen.hristev@...rochip.com>
---
.../bindings/media/snps,dw-csi.yaml | 149 ++++++++++++++++++
1 file changed, 149 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/snps,dw-csi.yaml
diff --git a/Documentation/devicetree/bindings/media/snps,dw-csi.yaml b/Documentation/devicetree/bindings/media/snps,dw-csi.yaml
new file mode 100644
index 000000000000..439eadc8e517
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/snps,dw-csi.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/snps,dw-csi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare CSI-2 Host controller (csi2host)
+
+maintainers:
+ - Eugen Hristev <eugen.hristev@...rochip.com>
+
+description:
+ CSI2HOST is used to receive image coming from an MIPI CSI-2 compatible
+ camera. It will convert the incoming CSI-2 stream into a dedicated
+ interface called the Synopsys IDI (Image Data Interface).
+ This interface is a 32-bit SoC internal only, and can be assimilated
+ with a CSI-2 interface.
+
+properties:
+ compatible:
+ const: snps,dw-csi
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ description:
+ CSI2HOST can have two clocks connected. One clock is the
+ peripheral clock for the inside functionality of the hardware block.
+ This is named 'perclk'. The second clock can be the phy clock,
+ which is used to clock the phy via an internal link.
+ This clock is named 'phyclk', phy clock.
+ items:
+ - const: perclk
+ - const: phyclk
+
+ phys:
+ maxItems: 1
+ description: MIPI D-PHY
+
+ phy-names:
+ items:
+ - const: dphy
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port node, single endpoint describing the input port.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+ description: Endpoint connected to input device
+
+ properties:
+ bus-type:
+ const: 4
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+ items:
+ maximum: 4
+
+ clock-lanes:
+ maxItems: 1
+
+ remote-endpoint: true
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Output port node, single endpoint describing the output port.
+
+ properties:
+ endpoint:
+ unevaluatedProperties: false
+ $ref: video-interfaces.yaml#
+ description: Endpoint connected to output device
+
+ properties:
+ bus-type:
+ const: 4
+
+ remote-endpoint: true
+
+ required:
+ - port@0
+ - port@1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - ports
+
+examples:
+ - |
+ csi2: csi2@...0 {
+ compatible = "snps,dw-csi";
+ reg = <0x03000 0x7FF>;
+ phys = <&mipi_dphy_rx>;
+ phy-names = "dphy";
+ resets = <&dw_rst 1>;
+ interrupts = <2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi_ep1: endpoint {
+ bus-type = <4>; /* MIPI CSI2 D-PHY */
+ remote-endpoint = <&camera_1>;
+ data-lanes = <1 2>;
+ clock-lanes = <0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csi_ep2: endpoint {
+ remote-endpoint = <&idi_receiver>;
+ bus-type = <4>;
+ };
+ };
+ };
+ };
+
+...
--
2.25.1
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