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Message-ID: <1bb4e2c3-3f6f-c161-ba7b-8e96f100f926@quicinc.com>
Date: Fri, 16 Dec 2022 12:51:52 -0800
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
To: Marijn Suijten <marijn.suijten@...ainline.org>,
<phone-devel@...r.kernel.org>, Rob Clark <robdclark@...il.com>,
"Dmitry Baryshkov" <dmitry.baryshkov@...aro.org>,
Vinod Koul <vkoul@...nel.org>
CC: <~postmarketos/upstreaming@...ts.sr.ht>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Martin Botka <martin.botka@...ainline.org>,
Jami Kettunen <jami.kettunen@...ainline.org>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
"Stephen Boyd" <swboyd@...omium.org>,
Bjorn Andersson <andersson@...nel.org>,
"Jessica Zhang" <quic_jesszhan@...cinc.com>,
Ville Syrjälä <ville.syrjala@...ux.intel.com>,
Kuogee Hsieh <quic_khsieh@...cinc.com>,
"Jani Nikula" <jani.nikula@...el.com>,
sunliming <sunliming@...inos.cn>,
"Sam Ravnborg" <sam@...nborg.org>,
Haowen Bai <baihaowen@...zu.com>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Loic Poulain <loic.poulain@...aro.org>,
"Vinod Polimera" <quic_vpolimer@...cinc.com>,
Douglas Anderson <dianders@...omium.org>,
Vladimir Lypak <vladimir.lypak@...il.com>,
<linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH 1/6] drm/msm/dpu1: Implement DSC binding to PP block
for CTL V1
On 12/13/2022 3:22 PM, Marijn Suijten wrote:
> All V1 CTL blocks (active CTLs) explicitly bind the pixel output from a
> DSC block to a PINGPONG block by setting the PINGPONG idx in a DSC
> hardware register.
>
> Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 9 +++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 27 +++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 4 +++
> 4 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 9c6817b5a194..c17ac85eb447 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1830,6 +1830,9 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> if (hw_pp->ops.setup_dsc)
> hw_pp->ops.setup_dsc(hw_pp);
>
> + if (hw_dsc->ops.dsc_bind_pingpong_blk)
> + hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, true, hw_pp->idx);
> +
> if (hw_pp->ops.enable_dsc)
> hw_pp->ops.enable_dsc(hw_pp);
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index c160dae95a69..96f849907aa2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -268,6 +268,15 @@ enum {
> DPU_VBIF_MAX
> };
>
> +/**
> + * DSC features
> + * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets
> + * the pixel output from this DSC.
> + */
> +enum {
> + DPU_DSC_OUTPUT_CTRL = 0x1,
> +};
> +
> /**
> * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU
> * @name: string name for debug purposes
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> index 3662df698dae..619926da1441 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> @@ -29,6 +29,8 @@
> #define DSC_RANGE_MAX_QP 0x0B0
> #define DSC_RANGE_BPG_OFFSET 0x0EC
>
> +#define DSC_CTL(m) (0x1800 - 0x3FC * (m - DSC_0))
> +
> static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
> {
> struct dpu_hw_blk_reg_map *c = &dsc->hw;
> @@ -150,6 +152,29 @@ static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
> }
> }
>
> +static void dpu_hw_dsc_bind_pingpong_blk(
> + struct dpu_hw_dsc *hw_dsc,
> + bool enable,
> + const enum dpu_pingpong pp)
> +{
> + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
> + int mux_cfg = 0xF;
> + u32 dsc_ctl_offset;
> +
> + dsc_ctl_offset = DSC_CTL(hw_dsc->idx);
> +
> + if (enable)
> + mux_cfg = (pp - PINGPONG_0) & 0x7;
> +
> + DRM_DEBUG_KMS("%s dsc:%d %s pp:%d\n",
> + enable ? "Binding" : "Unbinding",
> + hw_dsc->idx - DSC_0,
> + enable ? "to" : "from",
> + pp - PINGPONG_0);
> +
> + DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg);
> +}
> +
> static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
> const struct dpu_mdss_cfg *m,
> void __iomem *addr,
> @@ -174,6 +199,8 @@ static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
> ops->dsc_disable = dpu_hw_dsc_disable;
> ops->dsc_config = dpu_hw_dsc_config;
> ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
> + if (cap & BIT(DPU_DSC_OUTPUT_CTRL))
> + ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
> };
>
> struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> index c0b77fe1a696..ae9b5db53d7f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> @@ -42,6 +42,10 @@ struct dpu_hw_dsc_ops {
> */
> void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
> struct drm_dsc_config *dsc);
> +
> + void (*dsc_bind_pingpong_blk)(struct dpu_hw_dsc *hw_dsc,
> + bool enable,
> + enum dpu_pingpong pp);
> };
>
> struct dpu_hw_dsc {
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