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Message-Id: <20221216230934.2478345-3-f.fainelli@gmail.com>
Date: Fri, 16 Dec 2022 15:09:34 -0800
From: Florian Fainelli <f.fainelli@...il.com>
To: linux-kernel@...r.kernel.org
Cc: Florian Fainelli <f.fainelli@...il.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>, Rob Herring <robh@...nel.org>,
Doug Berger <opendmb@...il.com>,
Jason Cooper <jason@...edaemon.net>,
linux-mips@...r.kernel.org (open list:BROADCOM BMIPS MIPS ARCHITECTURE),
linux-arm-kernel@...ts.infradead.org (moderated list:BROADCOM BCM7XXX
ARM ARCHITECTURE)
Subject: [PATCH 2/2] irqchip/irq-bcm7120-l2: Set IRQ_LEVEL for level triggered interrupts
When support for the interrupt controller was added with a5042de2688d,
we forgot to update the flags to be set to contain IRQ_LEVEL. While the
flow handler is correct, the output from /proc/interrupts does not show
such interrupts as being level triggered when they are, correct that.
Fixes: a5042de2688d ("irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controller")
Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
---
drivers/irqchip/irq-bcm7120-l2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c
index bb6609cebdbc..1e9dab6e0d86 100644
--- a/drivers/irqchip/irq-bcm7120-l2.c
+++ b/drivers/irqchip/irq-bcm7120-l2.c
@@ -279,7 +279,8 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn,
flags |= IRQ_GC_BE_IO;
ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
- dn->full_name, handle_level_irq, clr, 0, flags);
+ dn->full_name, handle_level_irq, clr,
+ IRQ_LEVEL, flags);
if (ret) {
pr_err("failed to allocate generic irq chip\n");
goto out_free_domain;
--
2.34.1
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