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Message-ID: <20221219094233.179153-4-xingyu.wu@starfivetech.com>
Date: Mon, 19 Dec 2022 17:42:33 +0800
From: Xingyu Wu <xingyu.wu@...rfivetech.com>
To: <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-watchdog@...r.kernel.org>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC: Rob Herring <robh+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Philipp Zabel <p.zabel@...gutronix.de>,
Xingyu Wu <xingyu.wu@...rfivetech.com>,
Samin Guo <samin.guo@...rfivetech.com>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH v2 3/3] riscv: dts: starfive: jh7110: Add watchdog node
Add the watchdog node for the Starfive JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index c22e8f1d2640..cf981dce5bb9 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -433,5 +433,16 @@ uart5: serial@...20000 {
reg-shift = <2>;
status = "disabled";
};
+
+ wdog: watchdog@...70000 {
+ compatible = "starfive,jh7110-wdt";
+ reg = <0x0 0x13070000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
+ <&syscrg JH7110_SYSCLK_WDT_CORE>;
+ clock-names = "apb", "core";
+ resets = <&syscrg JH7110_SYSRST_WDT_APB>,
+ <&syscrg JH7110_SYSRST_WDT_CORE>;
+ reset-names = "apb", "core";
+ };
};
};
--
2.25.1
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