linux-kernel - Re: [PATCH v3 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

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Date:   Mon, 19 Dec 2022 11:57:14 +0100
From:   Heiko Stübner <heiko@...ech.de>
To:     Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        linux-sunxi@...ts.linux.dev, Palmer Dabbelt <palmer@...belt.com>,
        Conor Dooley <conor@...nel.org>,
        linux-riscv@...ts.infradead.org,
        Samuel Holland <samuel@...lland.org>
Cc:     Jisheng Zhang <jszhang@...nel.org>, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        linux-arm-kernel@...ts.infradead.org,
        Andre Przywara <andre.przywara@....com>,
        Samuel Holland <samuel@...lland.org>,
        Palmer Dabbelt <palmer@...osinc.com>,
        Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v3 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

Am Donnerstag, 8. Dezember 2022, 10:02:29 CET schrieb Samuel Holland:
> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
> 
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
> 
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
> 
> The devicetrees are organized to minimize duplication:
>  - Common perhiperals are described in sunxi-d1s-t113.dtsi
>  - DSP-related peripherals are described in sunxi-d1-t113.dtsi
>  - RISC-V specific hardware is described in sun20i-d1s.dtsi
>  - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
> 
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
> 
> Acked-by: Jernej Skrabec <jernej.skrabec@...il.com>
> Acked-by: Palmer Dabbelt <palmer@...osinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> Tested-by: Heiko Stuebner <heiko.stuebner@...ll.eu>
> Signed-off-by: Samuel Holland <samuel@...lland.org>

after spending some more time looking at the devicetree, I'm pretty
confident that it looks ok, so also

Reviewed-by: Heiko Stuebner <heiko.stuebner@...ll.eu>