[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAFBinCAfF-=776E3k=NnhaG+rMCp3b=WbjkN=RKGG8vM3Cn-3Q@mail.gmail.com>
Date: Mon, 19 Dec 2022 12:00:15 +0100
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: Carlo Caione <ccaione@...libre.com>
Cc: David Airlie <airlied@...il.com>,
Jerome Brunet <jbrunet@...libre.com>,
Daniel Vetter <daniel@...ll.ch>,
Kevin Hilman <khilman@...libre.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
linux-amlogic@...ts.infradead.org, dri-devel@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH] drm/meson: Reduce the FIFO lines held when AFBC is not used
Hi Carlo,
On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@...libre.com> wrote:
>
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
On the 32-bit SoCs (for which VPU support is not upstream yet) it has
caused screen tearing instead of shifting the image.
> Conditionally increase the number of lines held after vsync only for
> SoCs using AFBC, leaving the default value for all the others.
That was also my approach (for a not-yet-upstream patch).
Since it's affecting already supported SoCs I suggest adding
"Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
is applying the patch).
Acked-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Powered by blists - more mailing lists