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Message-ID: <167156771008.1021954.965078236008496413.robh@kernel.org>
Date: Tue, 20 Dec 2022 14:21:50 -0600
From: Rob Herring <robh@...nel.org>
To: Hal Feng <hal.feng@...rfivetech.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
linux-riscv@...ts.infradead.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Michael Turquette <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Marc Zyngier <maz@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Ben Dooks <ben.dooks@...ive.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Albert Ou <aou@...s.berkeley.edu>,
Palmer Dabbelt <palmer@...belt.com>,
Conor Dooley <conor@...nel.org>
Subject: Re: [PATCH v3 4/7] dt-bindings: sifive,ccache0: Support StarFive
JH7110 SoC
On Tue, 20 Dec 2022 09:12:44 +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@...il.dk>
>
> This cache controller is also used on the StarFive JH7110 SoC.
>
> Signed-off-by: Emil Renner Berthing <kernel@...il.dk>
> Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> ---
> .../devicetree/bindings/riscv/sifive,ccache0.yaml | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@...nel.org>
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