lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Tue, 20 Dec 2022 21:17:46 +0530
From:   Manjunatha Venkatesh <manjunatha.venkatesh@....com>
To:     linux-kernel@...r.kernel.org, gregkh@...uxfoundation.org,
        will@...nel.org, axboe@...nel.dk, robh+dt@...nel.org
Cc:     mb@...htnvm.io, ckeepax@...nsource.cirrus.com, arnd@...db.d,
        manjunatha.venkatesh@....com, mst@...hat.com, javier@...igon.com,
        mikelley@...rosoft.com, jasowang@...hat.com,
        sunilmut@...rosoft.com, bjorn.andersson@...aro.org,
        krzysztof.kozlowski+dt@...aro.org, devicetree@...r.kernel.org,
        ashish.deshpande@....com, rvmanjumce@...il.com,
        Kwame Adwere <kwame.adwere@....com>
Subject: [PATCH v6 1/2] dt-bindings: uwb: Device tree information for Nxp SR1XX SOCs

Ultra-wideband (UWB) is a short-range wireless communication protocol.

NXP has SR1XX family of UWB Subsystems (UWBS) devices. SR1XX SOCs
are FiRa Compliant. SR1XX SOCs are flash less devices and they need
Firmware Download on every device boot. More details on the SR1XX Family
can be found at https://www.nxp.com/products/:UWB-TRIMENSION

The sr1xx driver work the SR1XX Family of UWBS, and uses UWB Controller
Interface (UCI).  The corresponding details are available in the FiRa
Consortium Website (https://www.firaconsortium.org/).

Link: https://lore.kernel.org/r/425858dc-59fe-2311-61ae-3b6dc77a2576@nxp.com
Signed-off-by: Manjunatha Venkatesh <manjunatha.venkatesh@....com>
Signed-off-by: Kwame Adwere <kwame.adwere@....com>
---
Changes since v5:
  - Moved ioctl command definitions into header file.
  - Version 5 patch review comments addressed.
  - Corporate lawyer sign-off updated.

 .../bindings/uwb/nxp,uwb-sr1xx.yaml           | 65 +++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/uwb/nxp,uwb-sr1xx.yaml

diff --git a/Documentation/devicetree/bindings/uwb/nxp,uwb-sr1xx.yaml b/Documentation/devicetree/bindings/uwb/nxp,uwb-sr1xx.yaml
new file mode 100644
index 000000000000..2a1caa661633
--- /dev/null
+++ b/Documentation/devicetree/bindings/uwb/nxp,uwb-sr1xx.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/uwb/nxp,uwb-sr1xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:  NXP SR1XX SOC family of Ultra Wide Band(UWB) device bindings
+
+description: The nxp-sr1xx driver works for the NXP SR1XX series of Ultra Wide
+    Band devices namely, SR150 and SR100T devices, and uses UWB Controller Interface (UCI).
+    The corresponding details are available in the FiRa Consortium Website.
+    (https://www.firaconsortium.org/). More details on the SR1XX Family can be
+    found at https://www.nxp.com/products/:UWB-TRIMENSION
+
+maintainers:
+  - Manjunatha Venkatesh <manjunatha.venkatesh@....com>
+
+properties:
+  compatible:
+    enum:
+      - nxp,sr1xx
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 45000000
+
+required:
+  - compatible
+  - reg
+  - spi-max-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    /* for Raspberry Pi with pin control stuff for GPIO irq */
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/gpio/gpio.h>
+
+    fragment@1 {
+        target = <&spi0>;
+        spi {
+            /* needed to avoid dtc warning */
+            #address-cells = <1>;
+            #size-cells = <0>;
+            interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+            status = "enabled";
+
+            sr1xx: sr1xx@0 {
+                compatible = "nxp,sr1xx";
+                reg = <0>;    /* CE0 */
+                /* GPIO_24 (PIN 18) Host Irq*/
+                nxp,sr1xx-irq-gpios = <&gpio 24 0>;
+                /* GPIO_18(PIN 12) Chip Enable*/
+                nxp,sr1xx-ce-gpios = <&gpio 18 0>;
+                /* GPIO_23(PIN 16) Read Indication from Host to SR1xx*/
+                nxp,sr1xx-ri-gpios = <&gpio 23 0>;
+                /*max supported frequency */
+                spi-max-frequency = <20000000>;
+            };
+        };
+    };
-- 
2.38.1

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ