linux-kernel - Re: [PATCH v1 2/3] ASoC: SOF: mediatek: Support mt8188 platform

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Message-ID: <31b2946b-d4f2-5e5b-a107-45b3454c601b@collabora.com>
Date:   Thu, 22 Dec 2022 12:09:34 +0100
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Tinghan Shen <tinghan.shen@...iatek.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
        Liam Girdwood <lgirdwood@...il.com>,
        Peter Ujfalusi <peter.ujfalusi@...ux.intel.com>,
        Bard Liao <yung-chuan.liao@...ux.intel.com>,
        Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>,
        Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
        Daniel Baluta <daniel.baluta@....com>,
        Mark Brown <broonie@...nel.org>,
        Jaroslav Kysela <perex@...ex.cz>,
        Takashi Iwai <tiwai@...e.com>,
        Chunxu Li <chunxu.li@...iatek.com>,
        Dan Carpenter <error27@...il.com>,
        YC Hung <yc.hung@...iatek.com>,
        Allen-KH Cheng <Allen-KH.Cheng@...iatek.com>
Cc:     devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        sound-open-firmware@...a-project.org, alsa-devel@...a-project.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v1 2/3] ASoC: SOF: mediatek: Support mt8188 platform

Il 22/12/22 08:21, Tinghan Shen ha scritto:
> Add support of SOF on MediaTek MT8188 SoC.
> MT8188 ADSP integrates with a single core Cadence HiFi-5 DSP.
> The IPC communication between AP and DSP is based on shared DRAM and
> mailbox interrupt.
> 
> The change in the mt8186.h is compatible on both mt8186 and
> mt8188. The register controls booting the DSP core with the
> default address or the user specified address. Both mt8186
> and mt8188 should boot with the user specified boot in the driver.
> The usage of the register is the same on both SoC, but the
> control bit is different on mt8186 and mt8188, which is bit 1 on mt8186
> and bit 0 on mt8188. Configure the redundant bit has noside effect
> on both SoCs.
> 
> Signed-off-by: Tinghan Shen <tinghan.shen@...iatek.com>
> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@...ux.intel.com>
> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>
> ---
>   sound/soc/sof/mediatek/mt8186/mt8186.c | 17 +++++++++++++++++
>   sound/soc/sof/mediatek/mt8186/mt8186.h |  3 ++-
>   2 files changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.c b/sound/soc/sof/mediatek/mt8186/mt8186.c
> index 79da25725987..af0dfc2fc4cc 100644
> --- a/sound/soc/sof/mediatek/mt8186/mt8186.c
> +++ b/sound/soc/sof/mediatek/mt8186/mt8186.c
> @@ -625,8 +625,25 @@ static const struct sof_dev_desc sof_of_mt8186_desc = {
>   	.ops = &sof_mt8186_ops,
>   };
>   
> +static const struct sof_dev_desc sof_of_mt8188_desc = {
> +	.ipc_supported_mask	= BIT(SOF_IPC),
> +	.ipc_default		= SOF_IPC,
> +	.default_fw_path = {
> +		[SOF_IPC] = "mediatek/sof",
> +	},
> +	.default_tplg_path = {
> +		[SOF_IPC] = "mediatek/sof-tplg",
> +	},
> +	.default_fw_filename = {
> +		[SOF_IPC] = "sof-mt8188.ri",
> +	},
> +	.nocodec_tplg_filename = "sof-mt8188-nocodec.tplg",
> +	.ops = &sof_mt8186_ops,
> +};
> +
>   static const struct of_device_id sof_of_mt8186_ids[] = {
>   	{ .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc},
> +	{ .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc},
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids);
> diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.h b/sound/soc/sof/mediatek/mt8186/mt8186.h
> index 98b2965e5ba6..886d687449e3 100644
> --- a/sound/soc/sof/mediatek/mt8186/mt8186.h
> +++ b/sound/soc/sof/mediatek/mt8186/mt8186.h
> @@ -52,7 +52,8 @@ struct snd_sof_dev;
>   #define ADSP_PRID			0x0
>   #define ADSP_ALTVEC_C0			0x04
>   #define ADSP_ALTVECSEL			0x0C
> -#define ADSP_ALTVECSEL_C0		BIT(1)
> +/* BIT(1) for mt8186. BIT(0) for mt8188 */

We can be clearer here:

#define MT8188_ADSP_ALTVECSEL_C0	BIT(0)
#define MT8186_ADSP_ALTVECSEL_C0	BIT(1)

/*
  * On MT8188, BIT(1) is not evaluated and on MT8186 BIT(0) is not evaluated:
  * We can simplify the driver by safely setting both bits regardless of the SoC.
  */
#define ADSP_ALTVECSEL_C0		(MT8188_ADSP_ALTVECSEL_C0 |
					 MT8186_ADSP_ALTVECSEL_C0)

...so that we don't have to check the commit history to understand what's going
on here, and it becomes clear that ALTVECSEL is not both bits, but one of them.

Cheers,
Angelo