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Message-ID: <9dec25fa-7bce-a715-b63e-0a71b5743e3d@linaro.org>
Date: Thu, 22 Dec 2022 15:06:53 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Emekcan Aras <emekcan.aras@....com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Liviu Dudau <liviu.dudau@....com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Sudeep Holla <sudeep.holla@....com>,
Miguel Silva <rui.silva@...aro.org>
Cc: linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 0/2] adds corstone500 device tree
On 22/12/2022 13:32, Emekcan Aras wrote:
> Adds device tree and correspondent binding for ARM Corstone500 reference
> solution.
>
> Thanks for the comments, and sorry for the late reply. Most of the comments are
> addressed except one.
>
> @Krzysztof Kozlowski: Thanks a lot for the comments. I've tried to fixed all of
> them. Just have one question regarding having no dtsi or compatible platform.
> Corstone500 is a reference hardware design, however there is no silicon solution
> from it yet. And from device tree perspective, both FPGA and FVP (virtual
> platform) implementations are identical(same addresses and same nodes, etc.).
> So we didn't want to create a seperate dtsi file. What would you recommend here
> ? Can you point me to a device tree from a similar platform?
Corstone1000 was accepted that way, so it is fine. I am just surprised
that if you are going to have silicons with it, there is no common
compatible and no shared DTSI.
What do you expect from customer? Re-implement and copy most of your DTS?
Best regards,
Krzysztof
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