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Message-Id: <20221222151319.122398-4-krzysztof.kozlowski@linaro.org>
Date: Thu, 22 Dec 2022 16:13:19 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Vinod Koul <vkoul@...nel.org>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Joel Selvaraj <joelselvaraj.oss@...il.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
Caleb Connolly <caleb@...nolly.tech>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Douglas Anderson <dianders@...omium.org>
Subject: [PATCH v4 4/4] arm64: dts: qcom: sdm845: do not customize SPI0 pin drive/bias
Each board should define pin drive/bias for used busses. All boards
using SPI0 (db845c and cheza) already do it, so drop the bias/drive
strength from SoC DTSI.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Reviewed-by: Douglas Anderson <dianders@...omium.org>
---
Cc: Doug Anderson <dianders@...omium.org>
Changes since v3:
1. Rb tag
Changes since v2:
1. New patch.
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index dcea535de9b7..cac70212cc2a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2785,8 +2785,6 @@ qup_i2c15_default: qup-i2c15-default-state {
qup_spi0_default: qup-spi0-default-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "qup0";
- drive-strength = <6>;
- bias-disable;
};
qup_spi1_default: qup-spi1-default-state {
--
2.34.1
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