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Message-ID: <e0d54746d023ace026ca1c0f9db3391ef83a8f88.camel@mediatek.com>
Date:   Thu, 22 Dec 2022 01:43:51 +0000
From:   Biao Huang (黄彪) <Biao.Huang@...iatek.com>
To:     "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "angelogioacchino.delregno@...labora.com" 
        <angelogioacchino.delregno@...labora.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>
CC:     "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        Macpaul Lin (林智斌) 
        <Macpaul.Lin@...iatek.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [RESEND PATCH v4] arm64: dts: mt8195: Add Ethernet controller

Dear Angelo,
	Thanks for your comments!

On Wed, 2022-12-21 at 11:13 +0100, AngeloGioacchino Del Regno wrote:
> Il 21/12/22 03:25, Biao Huang ha scritto:
> > Add Ethernet controller node for mt8195.
> > 
> > Signed-off-by: Biao Huang <biao.huang@...iatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 88
> > ++++++++++++++++++++
> >   arch/arm64/boot/dts/mediatek/mt8195.dtsi     | 86
> > +++++++++++++++++++
> >   2 files changed, 174 insertions(+)
> > 
> 
> ..snip..
> 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 5d31536f4c48..02112bbf2bdf 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1046,6 +1046,92 @@ spis1: spi@...1e000 {
> >   			status = "disabled";
> >   		};
> >   
> > +		eth: ethernet@...21000 {
> > +			compatible = "mediatek,mt8195-gmac",
> > "snps,dwmac-5.10a";
> > +			reg = <0 0x11021000 0 0x4000>;
> > +			interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			interrupt-names = "macirq";
> > +			clock-names = "axi",
> > +				      "apb",
> > +				      "mac_cg",
> 
> mac_cg goes as last clock, as specified in the binding.
> 
> Order: axi, apb, mac_main, ptp_ref, rmii_internal, mac_cg.
> 
> Please fix.
OK, will fix in next send.
> 
> Regards,
> Angelo
> 
> > +				      "mac_main",
> > +				      "ptp_ref",
> > +				      "rmii_internal";
> > +			clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
> > +				 <&pericfg_ao
> > CLK_PERI_AO_ETHERNET_BUS>,
> > +				 <&pericfg_ao
> > CLK_PERI_AO_ETHERNET_MAC>,
> > +				 <&topckgen CLK_TOP_SNPS_ETH_250M>,
> > +				 <&topckgen
> > CLK_TOP_SNPS_ETH_62P4M_PTP>,
> > +				 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
> 
> 

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