linux-kernel - Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree

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Date:   Fri, 23 Dec 2022 11:12:34 +0800
From:   Hal Feng <hal.feng@...rfivetech.com>
To:     Conor Dooley <conor@...nel.org>
CC:     <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        "Palmer Dabbelt" <palmer@...belt.com>,
        Rob Herring <robh+dt@...nel.org>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Ben Dooks <ben.dooks@...ive.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        "Thomas Gleixner" <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        "Philipp Zabel" <p.zabel@...gutronix.de>,
        Linus Walleij <linus.walleij@...aro.org>,
        Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110
 VisionFive 2 board device tree

On Tue, 20 Dec 2022 21:26:07 +0000, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@...il.dk>
> > 
> > Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> > which has version A and version B. Support booting and basic
> > clock/reset/pinctrl/uart drivers.
> > 
> > Signed-off-by: Emil Renner Berthing <kernel@...il.dk>
> > Co-developed-by: Jianlong Huang <jianlong.huang@...rfivetech.com>
> > Signed-off-by: Jianlong Huang <jianlong.huang@...rfivetech.com>
> > Co-developed-by: Hal Feng <hal.feng@...rfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> > ---
> >  arch/riscv/boot/dts/starfive/Makefile         |   1 +
> >  .../jh7110-starfive-visionfive-2-va.dts       |  13 ++
> >  .../jh7110-starfive-visionfive-2-vb.dts       |  13 ++
> >  .../jh7110-starfive-visionfive-2.dtsi         | 111 ++++++++++++++++++
> >  4 files changed, 138 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> >  create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> >  create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> > index 0ea1bc15ab30..79e925a4a227 100644
> > --- a/arch/riscv/boot/dts/starfive/Makefile
> > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > @@ -1,2 +1,3 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >  dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> > +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
> 
> Could you rebase on top of v6.2-rc1 when you submit your next version

Sure.

> squash this in please (unless Emil hates it):
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index c38a9ade7f48..b3744420253a 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,3 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-vb.dtb
> 
> I'd rather have more, but easier to read lines than long ones.

I'm fine with this change. If no objection, I will modify it.

Best regards,
Hal

> 
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > new file mode 100644
> > index 000000000000..c60280b89c73
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > @@ -0,0 +1,111 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@...il.dk>
> > + */
> > +
> > +/dts-v1/;
> > +#include "jh7110.dtsi"
> > +#include "jh7110-pinfunc.h"
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > +	aliases {
> > +		serial0 = &uart0;
> > +	};
> > +
> > +	chosen {
> > +		stdout-path = "serial0:115200n8";
> > +	};
> > +
> > +	cpus {
> > +		timebase-frequency = <4000000>;
> > +	};
> > +
> > +	memory@...00000 {
> > +		device_type = "memory";
> > +		reg = <0x0 0x40000000 0x1 0x0>;
> 
> Is this a good idea when you have SKUs with 2, 4 & 8 GiB of DDR?

The VisionFive 2 board only has 4GB version and 8GB version now. Before
linux startup, we will change this property in dtb through u-boot to
make sure the board can boot up with the correct memory size.

Best regards,
Hal

> 
> Anyways, I can't review this as I've got neither board nor
> documentation, so with the above stuff sorted out:
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> I'll not apply it until the clock binding header is in my tree.