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Message-ID: <8a1389f8-ec20-ae85-97b9-599f0c10b8b4@linaro.org>
Date:   Fri, 23 Dec 2022 09:58:07 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        andersson@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, bp@...en8.de,
        tony.luck@...el.com
Cc:     quic_saipraka@...cinc.com, konrad.dybcio@...aro.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        james.morse@....com, mchehab@...nel.org, rric@...nel.org,
        linux-edac@...r.kernel.org, quic_ppareek@...cinc.com,
        luca.weiss@...rphone.com, ahalaney@...hat.com, steev@...i.org
Subject: Re: [PATCH v4 02/16] dt-bindings: arm: msm: Fix register regions used
 for LLCC banks

On 22/12/2022 14:16, Manivannan Sadhasivam wrote:
> Register regions of the LLCC banks are located at different addresses.
> Currently, the binding just lists the LLCC0 base address and tries to
> cover all the banks using a single size. This is entirely wrong as there
> are other register regions that happen to lie inside the size covered by
> the binding such as the memory controller and holes.
> 
> So this needs to be fixed by specifying the base address of individual
> LLCC banks. This approach will break the existing users of this binding
> as the register regions are splitted and the drivers now cannot use
> LLCC0 register region for accessing rest of the banks (which is wrong
> anyway).
> 
> But considering the fact that the binding was wrong from the day one and
> also the device drivers going wrong by the binding, this breakage is
> acceptable.
> 
> Reported-by: Parikshit Pareek <quic_ppareek@...cinc.com>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Best regards,
Krzysztof

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