| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 27 Dec 2022 00:25:05 +0800
From: kernel test robot <lkp@...el.com>
To: George Shen <george.shen@....com>
Cc: oe-kbuild-all@...ts.linux.dev, linux-kernel@...r.kernel.org,
Alex Deucher <alexander.deucher@....com>,
Alvin Lee <Alvin.Lee2@....com>
Subject: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:217:17:
warning: variable 'cursor_bpp' set but not used
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 1b929c02afd37871d5afb9d498426f83432e71c2
commit: 57b014f664b46deafcd4f4d408416aae6c7e16b9 drm/amd/display: Fix calculation for cursor CAB allocation
date: 6 weeks ago
config: arm64-randconfig-r036-20221225
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=57b014f664b46deafcd4f4d408416aae6c7e16b9
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 57b014f664b46deafcd4f4d408416aae6c7e16b9
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/ mm//
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c: In function 'dcn32_calculate_cab_allocation':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:217:17: warning: variable 'cursor_bpp' set but not used [-Wunused-but-set-variable]
217 | uint8_t cursor_bpp = 0;
| ^~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:32,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:29:
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h: At top level:
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:137:22: warning: 'SYNAPTICS_DEVICE_ID' defined but not used [-Wunused-const-variable=]
137 | static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:134:17: warning: 'DP_SINK_BRANCH_DEV_NAME_7580' defined but not used [-Wunused-const-variable=]
134 | static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u";
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:132:22: warning: 'DP_SINK_DEVICE_STR_ID_2' defined but not used [-Wunused-const-variable=]
132 | static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5};
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:131:22: warning: 'DP_SINK_DEVICE_STR_ID_1' defined but not used [-Wunused-const-variable=]
131 | static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3};
| ^~~~~~~~~~~~~~~~~~~~~~~
vim +/cursor_bpp +217 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c
235c67634230b0 Aurabindo Pillai 2022-02-23 201
235c67634230b0 Aurabindo Pillai 2022-02-23 202
235c67634230b0 Aurabindo Pillai 2022-02-23 203 /* This function loops through every surface that needs to be cached in CAB for SS,
235c67634230b0 Aurabindo Pillai 2022-02-23 204 * and calculates the total number of ways required to store all surfaces (primary,
235c67634230b0 Aurabindo Pillai 2022-02-23 205 * meta, cursor).
235c67634230b0 Aurabindo Pillai 2022-02-23 206 */
235c67634230b0 Aurabindo Pillai 2022-02-23 207 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
235c67634230b0 Aurabindo Pillai 2022-02-23 208 {
2fd23d467d4fb4 Josip Pavic 2022-09-23 209 int i, j;
235c67634230b0 Aurabindo Pillai 2022-02-23 210 struct dc_stream_state *stream = NULL;
235c67634230b0 Aurabindo Pillai 2022-02-23 211 struct dc_plane_state *plane = NULL;
235c67634230b0 Aurabindo Pillai 2022-02-23 212 uint32_t cursor_size = 0;
235c67634230b0 Aurabindo Pillai 2022-02-23 213 uint32_t total_lines = 0;
235c67634230b0 Aurabindo Pillai 2022-02-23 214 uint32_t lines_per_way = 0;
525a65c77db51c Alvin Lee 2022-09-14 215 uint8_t num_ways = 0;
525a65c77db51c Alvin Lee 2022-09-14 216 uint8_t bytes_per_pixel = 0;
525a65c77db51c Alvin Lee 2022-09-14 @217 uint8_t cursor_bpp = 0;
525a65c77db51c Alvin Lee 2022-09-14 218 uint16_t mblk_width = 0;
525a65c77db51c Alvin Lee 2022-09-14 219 uint16_t mblk_height = 0;
525a65c77db51c Alvin Lee 2022-09-14 220 uint16_t mall_alloc_width_blk_aligned = 0;
525a65c77db51c Alvin Lee 2022-09-14 221 uint16_t mall_alloc_height_blk_aligned = 0;
525a65c77db51c Alvin Lee 2022-09-14 222 uint16_t num_mblks = 0;
525a65c77db51c Alvin Lee 2022-09-14 223 uint32_t bytes_in_mall = 0;
525a65c77db51c Alvin Lee 2022-09-14 224 uint32_t cache_lines_used = 0;
525a65c77db51c Alvin Lee 2022-09-14 225 uint32_t cache_lines_per_plane = 0;
235c67634230b0 Aurabindo Pillai 2022-02-23 226
525a65c77db51c Alvin Lee 2022-09-14 227 for (i = 0; i < dc->res_pool->pipe_count; i++) {
525a65c77db51c Alvin Lee 2022-09-14 228 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
235c67634230b0 Aurabindo Pillai 2022-02-23 229
525a65c77db51c Alvin Lee 2022-09-14 230 if (!pipe->stream || !pipe->plane_state ||
525a65c77db51c Alvin Lee 2022-09-14 231 pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED ||
525a65c77db51c Alvin Lee 2022-09-14 232 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
235c67634230b0 Aurabindo Pillai 2022-02-23 233 continue;
235c67634230b0 Aurabindo Pillai 2022-02-23 234
525a65c77db51c Alvin Lee 2022-09-14 235 bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4;
525a65c77db51c Alvin Lee 2022-09-14 236 mblk_width = DCN3_2_MBLK_WIDTH;
525a65c77db51c Alvin Lee 2022-09-14 237 mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE;
235c67634230b0 Aurabindo Pillai 2022-02-23 238
525a65c77db51c Alvin Lee 2022-09-14 239 /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) -
525a65c77db51c Alvin Lee 2022-09-14 240 * FLOOR(vp_x_start, blk_width)
525a65c77db51c Alvin Lee 2022-09-14 241 *
525a65c77db51c Alvin Lee 2022-09-14 242 * mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c
525a65c77db51c Alvin Lee 2022-09-14 243 */
525a65c77db51c Alvin Lee 2022-09-14 244 mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x +
5caa63c7b7e1cb Alvin Lee 2022-09-15 245 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) -
525a65c77db51c Alvin Lee 2022-09-14 246 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width);
235c67634230b0 Aurabindo Pillai 2022-02-23 247
525a65c77db51c Alvin Lee 2022-09-14 248 /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) -
525a65c77db51c Alvin Lee 2022-09-14 249 * FLOOR(vp_y_start, blk_height)
525a65c77db51c Alvin Lee 2022-09-14 250 *
525a65c77db51c Alvin Lee 2022-09-14 251 * mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c
525a65c77db51c Alvin Lee 2022-09-14 252 */
525a65c77db51c Alvin Lee 2022-09-14 253 mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y +
5caa63c7b7e1cb Alvin Lee 2022-09-15 254 pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) -
525a65c77db51c Alvin Lee 2022-09-14 255 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height);
525a65c77db51c Alvin Lee 2022-09-14 256
525a65c77db51c Alvin Lee 2022-09-14 257 num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) *
525a65c77db51c Alvin Lee 2022-09-14 258 ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);
525a65c77db51c Alvin Lee 2022-09-14 259
525a65c77db51c Alvin Lee 2022-09-14 260 /* For DCC:
525a65c77db51c Alvin Lee 2022-09-14 261 * meta_num_mblk = CEILING(full_mblk_width_ub_l*full_mblk_height_ub_l*Bpe/256/mblk_bytes, 1)
525a65c77db51c Alvin Lee 2022-09-14 262 */
525a65c77db51c Alvin Lee 2022-09-14 263 if (pipe->plane_state->dcc.enable)
525a65c77db51c Alvin Lee 2022-09-14 264 num_mblks += (mall_alloc_width_blk_aligned * mall_alloc_width_blk_aligned * bytes_per_pixel +
525a65c77db51c Alvin Lee 2022-09-14 265 (256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES);
525a65c77db51c Alvin Lee 2022-09-14 266
525a65c77db51c Alvin Lee 2022-09-14 267 bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES;
525a65c77db51c Alvin Lee 2022-09-14 268
525a65c77db51c Alvin Lee 2022-09-14 269 /* (cache lines used is total bytes / cache_line size. Add +2 for worst case alignment
525a65c77db51c Alvin Lee 2022-09-14 270 * (MALL is 64-byte aligned)
525a65c77db51c Alvin Lee 2022-09-14 271 */
525a65c77db51c Alvin Lee 2022-09-14 272 cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2;
525a65c77db51c Alvin Lee 2022-09-14 273 cache_lines_used += cache_lines_per_plane;
235c67634230b0 Aurabindo Pillai 2022-02-23 274 }
235c67634230b0 Aurabindo Pillai 2022-02-23 275
235c67634230b0 Aurabindo Pillai 2022-02-23 276 // Include cursor size for CAB allocation
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 277 for (j = 0; j < dc->res_pool->pipe_count; j++) {
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 278 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[j];
a3cdb5d2c89c80 Aurabindo Pillai 2022-08-18 279 struct hubp *hubp = pipe->plane_res.hubp;
a3cdb5d2c89c80 Aurabindo Pillai 2022-08-18 280
a3cdb5d2c89c80 Aurabindo Pillai 2022-08-18 281 if (pipe->stream && pipe->plane_state && hubp)
a3cdb5d2c89c80 Aurabindo Pillai 2022-08-18 282 /* Find the cursor plane and use the exact size instead of
525a65c77db51c Alvin Lee 2022-09-14 283 using the max for calculation */
525a65c77db51c Alvin Lee 2022-09-14 284
a3cdb5d2c89c80 Aurabindo Pillai 2022-08-18 285 if (hubp->curs_attr.width > 0) {
57b014f664b46d George Shen 2022-11-01 286 cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
a3cdb5d2c89c80 Aurabindo Pillai 2022-08-18 287
525a65c77db51c Alvin Lee 2022-09-14 288 switch (pipe->stream->cursor_attributes.color_format) {
235c67634230b0 Aurabindo Pillai 2022-02-23 289 case CURSOR_MODE_MONO:
235c67634230b0 Aurabindo Pillai 2022-02-23 290 cursor_size /= 2;
525a65c77db51c Alvin Lee 2022-09-14 291 cursor_bpp = 4;
235c67634230b0 Aurabindo Pillai 2022-02-23 292 break;
235c67634230b0 Aurabindo Pillai 2022-02-23 293 case CURSOR_MODE_COLOR_1BIT_AND:
235c67634230b0 Aurabindo Pillai 2022-02-23 294 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
235c67634230b0 Aurabindo Pillai 2022-02-23 295 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
235c67634230b0 Aurabindo Pillai 2022-02-23 296 cursor_size *= 4;
525a65c77db51c Alvin Lee 2022-09-14 297 cursor_bpp = 4;
235c67634230b0 Aurabindo Pillai 2022-02-23 298 break;
235c67634230b0 Aurabindo Pillai 2022-02-23 299
235c67634230b0 Aurabindo Pillai 2022-02-23 300 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
235c67634230b0 Aurabindo Pillai 2022-02-23 301 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
235c67634230b0 Aurabindo Pillai 2022-02-23 302 cursor_size *= 8;
525a65c77db51c Alvin Lee 2022-09-14 303 cursor_bpp = 8;
235c67634230b0 Aurabindo Pillai 2022-02-23 304 break;
235c67634230b0 Aurabindo Pillai 2022-02-23 305 }
f6f76233bf506d Aurabindo Pillai 2022-08-18 306
525a65c77db51c Alvin Lee 2022-09-14 307 if (pipe->stream->cursor_position.enable && !dc->debug.alloc_extra_way_for_cursor &&
6eef3746058426 Alvin Lee 2022-09-01 308 cursor_size > 16384) {
525a65c77db51c Alvin Lee 2022-09-14 309 /* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1)
525a65c77db51c Alvin Lee 2022-09-14 310 */
57b014f664b46d George Shen 2022-11-01 311 cache_lines_used += (((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) /
57b014f664b46d George Shen 2022-11-01 312 DCN3_2_MALL_MBLK_SIZE_BYTES) * DCN3_2_MALL_MBLK_SIZE_BYTES) /
57b014f664b46d George Shen 2022-11-01 313 dc->caps.cache_line_size + 2;
525a65c77db51c Alvin Lee 2022-09-14 314 }
525a65c77db51c Alvin Lee 2022-09-14 315 break;
235c67634230b0 Aurabindo Pillai 2022-02-23 316 }
235c67634230b0 Aurabindo Pillai 2022-02-23 317 }
235c67634230b0 Aurabindo Pillai 2022-02-23 318
235c67634230b0 Aurabindo Pillai 2022-02-23 319 // Convert number of cache lines required to number of ways
235c67634230b0 Aurabindo Pillai 2022-02-23 320 total_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
235c67634230b0 Aurabindo Pillai 2022-02-23 321 lines_per_way = total_lines / dc->caps.cache_num_ways;
235c67634230b0 Aurabindo Pillai 2022-02-23 322 num_ways = cache_lines_used / lines_per_way;
235c67634230b0 Aurabindo Pillai 2022-02-23 323
235c67634230b0 Aurabindo Pillai 2022-02-23 324 if (cache_lines_used % lines_per_way > 0)
235c67634230b0 Aurabindo Pillai 2022-02-23 325 num_ways++;
235c67634230b0 Aurabindo Pillai 2022-02-23 326
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 327 for (i = 0; i < ctx->stream_count; i++) {
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 328 stream = ctx->streams[i];
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 329 for (j = 0; j < ctx->stream_status[i].plane_count; j++) {
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 330 plane = ctx->stream_status[i].plane_states[j];
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 331
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 332 if (stream->cursor_position.enable && plane &&
6eef3746058426 Alvin Lee 2022-09-01 333 dc->debug.alloc_extra_way_for_cursor &&
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 334 cursor_size > 16384) {
f6f76233bf506d Aurabindo Pillai 2022-08-18 335 /* Cursor caching is not supported since it won't be on the same line.
f6f76233bf506d Aurabindo Pillai 2022-08-18 336 * So we need an extra line to accommodate it. With large cursors and a single 4k monitor
f6f76233bf506d Aurabindo Pillai 2022-08-18 337 * this case triggers corruption. If we're at the edge, then dont trigger display refresh
f6f76233bf506d Aurabindo Pillai 2022-08-18 338 * from MALL. We only need to cache cursor if its greater that 64x64 at 4 bpp.
f6f76233bf506d Aurabindo Pillai 2022-08-18 339 */
f6f76233bf506d Aurabindo Pillai 2022-08-18 340 num_ways++;
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 341 /* We only expect one cursor plane */
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 342 break;
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 343 }
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 344 }
6420f4ca68fb9d Aurabindo Pillai 2022-08-19 345 }
525a65c77db51c Alvin Lee 2022-09-14 346 if (dc->debug.force_mall_ss_num_ways > 0) {
525a65c77db51c Alvin Lee 2022-09-14 347 num_ways = dc->debug.force_mall_ss_num_ways;
525a65c77db51c Alvin Lee 2022-09-14 348 }
235c67634230b0 Aurabindo Pillai 2022-02-23 349 return num_ways;
235c67634230b0 Aurabindo Pillai 2022-02-23 350 }
235c67634230b0 Aurabindo Pillai 2022-02-23 351
:::::: The code at line 217 was first introduced by commit
:::::: 525a65c77db51cf5d6c6d8e3f8d07efeb2270416 drm/amd/display: Update MALL SS NumWays calculation
:::::: TO: Alvin Lee <Alvin.Lee2@....com>
:::::: CC: Alex Deucher <alexander.deucher@....com>
--
0-DAY CI Kernel Test Service
https://01.org/lkp
View attachment "config" of type "text/plain" (152043 bytes)
Powered by blists - more mailing lists