linux-kernel - Re: [PATCH] LoongArch: Simplifying larch_insn_gen

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Message-ID: <CAAhV-H49QBCZNo-qUBR-oJ-5Oxbb8Dd7=fp5=7_+1FK_uR46qg@mail.gmail.com>
Date:   Tue, 27 Dec 2022 15:24:55 +0800
From:   Huacai Chen <chenhuacai@...nel.org>
To:     Youling Tang <tangyouling@...ngson.cn>
Cc:     WANG Xuerui <kernel@...0n.name>, loongarch@...ts.linux.dev,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] LoongArch: Simplifying larch_insn_gen_xxx implementation

Queued, thanks.

Huacai

On Fri, Dec 23, 2022 at 10:08 AM Youling Tang <tangyouling@...ngson.cn> wrote:
>
> Simplify larch_insn_gen_xxx implementation by reusing emit_xxx.
>
> Signed-off-by: Youling Tang <tangyouling@...ngson.cn>
> ---
>  arch/loongarch/include/asm/inst.h |  1 +
>  arch/loongarch/kernel/inst.c      | 45 +++++--------------------------
>  2 files changed, 8 insertions(+), 38 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/inst.h b/arch/loongarch/include/asm/inst.h
> index c00e1512d4fa..a463b518a636 100644
> --- a/arch/loongarch/include/asm/inst.h
> +++ b/arch/loongarch/include/asm/inst.h
> @@ -401,6 +401,7 @@ static inline void emit_##NAME(union loongarch_instruction *insn,   \
>  }
>
>  DEF_EMIT_REG0I26_FORMAT(b, b_op)
> +DEF_EMIT_REG0I26_FORMAT(bl, bl_op)
>
>  #define DEF_EMIT_REG1I20_FORMAT(NAME, OP)                              \
>  static inline void emit_##NAME(union loongarch_instruction *insn,      \
> diff --git a/arch/loongarch/kernel/inst.c b/arch/loongarch/kernel/inst.c
> index 512579d79b22..badc59087042 100644
> --- a/arch/loongarch/kernel/inst.c
> +++ b/arch/loongarch/kernel/inst.c
> @@ -58,7 +58,6 @@ u32 larch_insn_gen_nop(void)
>  u32 larch_insn_gen_b(unsigned long pc, unsigned long dest)
>  {
>         long offset = dest - pc;
> -       unsigned int immediate_l, immediate_h;
>         union loongarch_instruction insn;
>
>         if ((offset & 3) || offset < -SZ_128M || offset >= SZ_128M) {
> @@ -66,15 +65,7 @@ u32 larch_insn_gen_b(unsigned long pc, unsigned long dest)
>                 return INSN_BREAK;
>         }
>
> -       offset >>= 2;
> -
> -       immediate_l = offset & 0xffff;
> -       offset >>= 16;
> -       immediate_h = offset & 0x3ff;
> -
> -       insn.reg0i26_format.opcode = b_op;
> -       insn.reg0i26_format.immediate_l = immediate_l;
> -       insn.reg0i26_format.immediate_h = immediate_h;
> +       emit_b(&insn, offset >> 2);
>
>         return insn.word;
>  }
> @@ -82,7 +73,6 @@ u32 larch_insn_gen_b(unsigned long pc, unsigned long dest)
>  u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest)
>  {
>         long offset = dest - pc;
> -       unsigned int immediate_l, immediate_h;
>         union loongarch_instruction insn;
>
>         if ((offset & 3) || offset < -SZ_128M || offset >= SZ_128M) {
> @@ -90,15 +80,7 @@ u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest)
>                 return INSN_BREAK;
>         }
>
> -       offset >>= 2;
> -
> -       immediate_l = offset & 0xffff;
> -       offset >>= 16;
> -       immediate_h = offset & 0x3ff;
> -
> -       insn.reg0i26_format.opcode = bl_op;
> -       insn.reg0i26_format.immediate_l = immediate_l;
> -       insn.reg0i26_format.immediate_h = immediate_h;
> +       emit_bl(&insn, offset >> 2);
>
>         return insn.word;
>  }
> @@ -107,10 +89,7 @@ u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongar
>  {
>         union loongarch_instruction insn;
>
> -       insn.reg3_format.opcode = or_op;
> -       insn.reg3_format.rd = rd;
> -       insn.reg3_format.rj = rj;
> -       insn.reg3_format.rk = rk;
> +       emit_or(&insn, rd, rj, rk);
>
>         return insn.word;
>  }
> @@ -124,9 +103,7 @@ u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm)
>  {
>         union loongarch_instruction insn;
>
> -       insn.reg1i20_format.opcode = lu12iw_op;
> -       insn.reg1i20_format.rd = rd;
> -       insn.reg1i20_format.immediate = imm;
> +       emit_lu12iw(&insn, rd, imm);
>
>         return insn.word;
>  }
> @@ -135,9 +112,7 @@ u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm)
>  {
>         union loongarch_instruction insn;
>
> -       insn.reg1i20_format.opcode = lu32id_op;
> -       insn.reg1i20_format.rd = rd;
> -       insn.reg1i20_format.immediate = imm;
> +       emit_lu32id(&insn, rd, imm);
>
>         return insn.word;
>  }
> @@ -146,10 +121,7 @@ u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)
>  {
>         union loongarch_instruction insn;
>
> -       insn.reg2i12_format.opcode = lu52id_op;
> -       insn.reg2i12_format.rd = rd;
> -       insn.reg2i12_format.rj = rj;
> -       insn.reg2i12_format.immediate = imm;
> +       emit_lu52id(&insn, rd, rj, imm);
>
>         return insn.word;
>  }
> @@ -158,10 +130,7 @@ u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, unsigned l
>  {
>         union loongarch_instruction insn;
>
> -       insn.reg2i16_format.opcode = jirl_op;
> -       insn.reg2i16_format.rd = rd;
> -       insn.reg2i16_format.rj = rj;
> -       insn.reg2i16_format.immediate = (dest - pc) >> 2;
> +       emit_jirl(&insn, rj, rd, (dest - pc) >> 2);
>
>         return insn.word;
>  }
> --
> 2.37.3
>
>