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Message-ID: <Y6tceOCC+YFtSY6F@spud>
Date:   Tue, 27 Dec 2022 20:58:32 +0000
From:   Conor Dooley <conor@...nel.org>
To:     Hal Feng <hal.feng@...rfivetech.com>
Cc:     linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        Palmer Dabbelt <palmer@...belt.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Ben Dooks <ben.dooks@...ive.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Linus Walleij <linus.walleij@...aro.org>,
        Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110
 device tree

On Sun, Dec 25, 2022 at 10:31:41PM +0800, Hal Feng wrote:
> On Tue, 20 Dec 2022 21:31:43 +0000, Conor Dooley wrote:
> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> > > From: Emil Renner Berthing <kernel@...il.dk>
> > > 
> > > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > > Technology Ltd.
> > > 
> > > Signed-off-by: Emil Renner Berthing <kernel@...il.dk>
> > > Co-developed-by: Jianlong Huang <jianlong.huang@...rfivetech.com>
> > > Signed-off-by: Jianlong Huang <jianlong.huang@...rfivetech.com>
> > > Co-developed-by: Hal Feng <hal.feng@...rfivetech.com>
> > > Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> > > ---

> > > +		gpio: gpio@...40000 {
> > 
> > > +		gpioa: gpio@...20000 {
> > 
> > Out of curiousity, why gpio & gpioa?
> 
> Oh, is it easier to read if I change "gpio" and "gpioa"
> to "sysgpio" and "aongpio"? Thanks.

I think those would be more reader friendly, that's for sure.


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