linux-kernel - Re: [PATCH] irqchip: gic-v3: Handle failure case of CPU enters low power state

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Wed, 28 Dec 2022 16:50:18 +0530
From:   Pavan Kondeti <quic_pkondeti@...cinc.com>
To:     Marc Zyngier <maz@...nel.org>
CC:     Pavan Kondeti <quic_pkondeti@...cinc.com>,
        Yogesh Lal <quic_ylal@...cinc.com>, <tglx@...utronix.de>,
        <linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>
Subject: Re: [PATCH] irqchip: gic-v3: Handle failure case of CPU enters low
 power state

On Wed, Dec 28, 2022 at 11:14:11AM +0000, Marc Zyngier wrote:
> On Tue, 27 Dec 2022 10:36:38 +0000,
> Pavan Kondeti <quic_pkondeti@...cinc.com> wrote:
> > 
> > Hi Yogesh,
> > 
> > On Fri, Dec 23, 2022 at 12:05:40AM +0530, Yogesh Lal wrote:
> > > When CPU enter in low power mode it disable the redistributor and
> > > Group1 interrupts. And re-initialise the system registers on wakeup.
> > > 
> > > But in case of failure to enter low power mode need to enable
> > > the redistributor and Group1 interrupts.
> > > 
> > > Signed-off-by: Yogesh Lal <quic_ylal@...cinc.com>
> > > ---
> > >  drivers/irqchip/irq-gic-v3.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> > > index 997104d..4904f00 100644
> > > --- a/drivers/irqchip/irq-gic-v3.c
> > > +++ b/drivers/irqchip/irq-gic-v3.c
> > > @@ -1376,7 +1376,7 @@ static int gic_retrigger(struct irq_data *data)
> > >  static int gic_cpu_pm_notifier(struct notifier_block *self,
> > >  			       unsigned long cmd, void *v)
> > >  {
> > > -	if (cmd == CPU_PM_EXIT) {
> > > +	if (cmd == CPU_PM_EXIT || cmd == CPU_PM_ENTER_FAILED) {
> > >  		if (gic_dist_security_disabled())
> > >  			gic_enable_redist(true);
> > >  		gic_cpu_sys_reg_init();
> > 
> > static int gic_cpu_pm_notifier(struct notifier_block *self,
> > 			       unsigned long cmd, void *v)
> > {
> > 	if (cmd == CPU_PM_EXIT) {
> > 		if (gic_dist_security_disabled())
> > 			gic_enable_redist(true);
> > 		gic_cpu_sys_reg_init();
> > 	} else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
> > 		gic_write_grpen1(0);
> > 		gic_enable_redist(false);
> > 	}
> > 	return NOTIFY_OK;
> > }
> > 
> > During CPU_PM_ENTER notification, we are not doing anything for the
> > !gic_dist_security_disabled() case. Since CPU_PM_ENTER_FAILED notification
> > arrive when CPU fails to power down, do we need to reinitialize the
> > system registers? IOW, should we do different handling for CPU_PM_ENTER_FAILED
> > based on gic_dist_security_disabled()?
> 
> What does it gain you apart from the extra complexity?
> 
Probably nothing. I am not very familiar with this part of code. If
gic_cpu_sys_reg_init() is written in such a way that it can be called even
when the CPU is not powered down, there is nothing to worry. The additional
complexity of dealing CPU_PM_EXIT vs CPU_PM_ENTER is pointless.

> gic_cpu_sys_reg_init() does very little, and makes sure we're always
> back into a sane state.
> 

Understood. Thanks for taking a look.

Thanks,
Pavan