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Message-Id: <20221228112456.31348-1-krzysztof.kozlowski@linaro.org>
Date: Wed, 28 Dec 2022 12:24:55 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH 1/2] arm64: dts: qcom: sm8350: add missing core_bi_pll_test_se GCC clock
The GCC bindings expect core_bi_pll_test_se clock input, even if it is
optional:
sm8350-mtp.dtb: clock-controller@...000: clock-names:2: 'core_bi_pll_test_se' was expected
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index d473194c968d..d5747bb467e0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -644,6 +644,7 @@ gcc: clock-controller@...000 {
#power-domain-cells = <1>;
clock-names = "bi_tcxo",
"sleep_clk",
+ "core_bi_pll_test_se",
"pcie_0_pipe_clk",
"pcie_1_pipe_clk",
"ufs_card_rx_symbol_0_clk",
@@ -661,6 +662,7 @@ gcc: clock-controller@...000 {
<0>,
<0>,
<0>,
+ <0>,
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>,
--
2.34.1
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