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Message-ID: <Y6yLMwhSypqp5+Ir@spud>
Date: Wed, 28 Dec 2022 18:30:11 +0000
From: Conor Dooley <conor@...nel.org>
To: Samuel Holland <samuel@...lland.org>
Cc: Palmer Dabbelt <palmer@...belt.com>,
Dmitry Osipenko <dmitry.osipenko@...labora.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@...el.com>,
Albert Ou <aou@...s.berkeley.edu>,
Anup Patel <apatel@...tanamicro.com>,
Atish Patra <atishp@...osinc.com>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
Heiko Stuebner <heiko@...ech.de>,
Kai-Heng Feng <kai.heng.feng@...onical.com>,
Luis Chamberlain <mcgrof@...nel.org>,
"Paul E. McKenney" <paulmck@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Petr Mladek <pmladek@...e.com>,
YueHaibing <yuehaibing@...wei.com>, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, tangmeng <tangmeng@...ontech.com>
Subject: Re: [PATCH 0/3] riscv: sbi: Switch to the sys-off handler API
Hey Samuel,
On Wed, Dec 28, 2022 at 10:19:12AM -0600, Samuel Holland wrote:
> I want to convert the axp20x PMIC poweroff handler to use the sys-off
> API, so it can be used as a fallback for if the SBI poweroff handler
> is unavailable. But the SBI poweroff handler still uses pm_power_off, so
> done alone, this would cause the axp20x callback to be called first,
> before the SBI poweroff handler has a chance to run.
>
> In order to prevent this change in behavior, the SBI poweroff handler
> needs to be converted to the sys-off API first, at a higher priority.
>
> This series performs the conversion, after accounting for the fact that
> the SBI poweroff handler is registered quite early during boot.
>
> The first patch is a dependency for both this series and the PSCI
> series[1], so I would like to get at least patch 1 merged soon.
>
> [1]: https://lore.kernel.org/lkml/20221105214841.7828-1-samuel@sholland.org/
>
>
> Samuel Holland (3):
> kernel/reboot: Use the static sys-off handler for any priority
> riscv: sbi: Share the code for unsupported extension warnings
> riscv: sbi: Switch to the sys-off handler API
Not what other stuff has reboot support, so I gave it a whirl on
PolarFire SoC & it seemed to work as expected:
Tested-by: Conor Dooley <conor.dooley@...rochip.com>
Thanks,
Conor.
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