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Message-Id: <20221229132731.1193713-1-krzysztof.kozlowski@linaro.org>
Date: Thu, 29 Dec 2022 14:27:31 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH] arm64: dts: qcom: sm8250: add cache size
Add full cache description to DTS to avoid:
1. "Early cacheinfo failed" warnings,
2. Cache topology detection which leads to early memory allocations and
"BUG: sleeping function called from invalid context" on PREEMPT_RT
kernel:
smp: Bringing up secondary CPUs ...
Detected VIPT I-cache on CPU1
BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:46
in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/1
preempt_count: 1, expected: 0
RCU nest depth: 1, expected: 1
3 locks held by swapper/1/0:
#0: ffff5e337eee5f18 (&pcp->lock){+.+.}-{3:3}, at: get_page_from_freelist+0x20c/0xffc
#1: ffffa9e24a900b18 (rcu_read_lock){....}-{1:3}, at: rt_spin_trylock+0x40/0xe4
#2: ffff5e337efc8918 (&zone->lock){+.+.}-{3:3}, at: rmqueue_bulk+0x54/0x720
irq event stamp: 0
Call trace:
__might_resched+0x17c/0x214
rt_spin_lock+0x5c/0x100
rmqueue_bulk+0x54/0x720
get_page_from_freelist+0xcfc/0xffc
__alloc_pages+0xec/0x1150
alloc_page_interleave+0x1c/0xd0
alloc_pages+0xec/0x160
new_slab+0x330/0x454
___slab_alloc+0x5b8/0xba0
__kmem_cache_alloc_node+0xf4/0x20c
__kmalloc+0x60/0x100
detect_cache_attributes+0x2a8/0x5a0
update_siblings_masks+0x28/0x300
store_cpu_topology+0x58/0x70
secondary_start_kernel+0xc8/0x154
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
The patch extends and depends in context on:
https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com
Cache sizes from publicly available data:
https://en.wikichip.org/wiki/qualcomm/snapdragon_800/865
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 4478bf0e7b22..4555345ee42e 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -111,10 +111,14 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-size = <0x20000>;
+ cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <0x400000>;
+ cache-unified;
};
};
};
@@ -137,6 +141,8 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-size = <0x20000>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -159,6 +165,8 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-size = <0x20000>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -181,6 +189,8 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-size = <0x20000>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -203,6 +213,8 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -225,6 +237,8 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
@@ -248,6 +262,8 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -270,6 +286,8 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
--
2.34.1
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