linux-kernel - Re: [PATCH] arm64: dts: qcom: sm8350: correct SDHCI interconnect arguments

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Date:   Thu, 29 Dec 2022 10:51:22 -0600
From:   Bjorn Andersson <andersson@...nel.org>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Andy Gross <agross@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sm8350: correct SDHCI interconnect
 arguments

On Tue, Dec 27, 2022 at 12:17:22PM +0100, Konrad Dybcio wrote:
> 
> 
> On 24.12.2022 22:43, Krzysztof Kozlowski wrote:
> > The interconnect providers accept only one argument (cells == 1), so fix
> > a copy&paste from SM8450:
> > 
> >   sm8350-hdk.dtb: mmc@...4000: interconnects: [[74, 9, 0], [75, 1, 0], [76, 2, 0], [77, 36, 0]] is too long
> > 
> > Fixes: 60477435e4de ("arm64: dts: qcom: sm8350: Add SDHCI2")
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> > 
> > ---
> This patch is correct, but if 8350 dts mdss [1] gets merged, it will become
> unnecessary, as it changes icc-cells to 2. Apply with caution i guess :D
> 

Seems reasonable to pick this fix for 6.2. Please help me remember to
check that [1] gets this right...


Thanks Krzysztof.

> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>

Thanks,
Bjorn

> 
> Konrad
> 
> [1] https://lore.kernel.org/linux-arm-msm/CAG3jFyuoXekXN48jAgXxLMy8yGAzK9oJH_1HHYAuRLBCzyordQ@mail.gmail.com/T/#mdd42dd600f0818ec103daa27c63add6700db86d3
> > 
> > Fix for v6.2-rc merge window.
> > ---
> >  arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > index 4fc15cc69b8c..0726930c9e28 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > @@ -2382,8 +2382,8 @@ sdhc_2: mmc@...4000 {
> >  				 <&rpmhcc RPMH_CXO_CLK>;
> >  			clock-names = "iface", "core", "xo";
> >  			resets = <&gcc GCC_SDCC2_BCR>;
> > -			interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
> > -					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
> > +			interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
> > +					<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
> >  			interconnect-names = "sdhc-ddr","cpu-sdhc";
> >  			iommus = <&apps_smmu 0x4a0 0x0>;
> >  			power-domains = <&rpmhpd SM8350_CX>;