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Message-ID: <1672407799-13768-3-git-send-email-quic_srivasam@quicinc.com>
Date: Fri, 30 Dec 2022 19:13:17 +0530
From: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
To: <swboyd@...omium.org>, <agross@...nel.org>, <andersson@...nel.org>,
<robh+dt@...nel.org>, <broonie@...nel.org>,
<quic_plai@...cinc.com>, <krzysztof.kozlowski+dt@...aro.org>,
<konrad.dybcio@...ainline.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_rohkumar@...cinc.com>
CC: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
Subject: [PATCH v2 2/4] dt-bindings: clock: qcom,sc7280-lpasscc: Add resets for audioreach
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for audioreach based SC7280 platforms.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@...cinc.com>
---
.../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 9c72b8e..40fc6ab 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -31,13 +31,18 @@ properties:
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
reg:
items:
- description: LPASS top-cc register
+ - description: LPASS reset-cgcr register
reg-names:
items:
- const: top_cc
+ - const: reset_cgcr
required:
- compatible
@@ -54,10 +59,11 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@...4000 {
compatible = "qcom,sc7280-lpasscc";
- reg = <0x03c04000 0x4>;
- reg-names = "top_cc";
+ reg = <0x03c04000 0x4>, <0x032a9000 0x1000>;
+ reg-names = "top_cc", "reset_cgcr";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
+ #reset-cells = <1>;
};
...
--
2.7.4
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