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Message-ID: <Y69DFFf0ZCvdA49f@linaro.org>
Date: Fri, 30 Dec 2022 21:59:16 +0200
From: Abel Vesa <abel.vesa@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>
Subject: Re: [PATCH v3 1/2] dt-bindings: pinctrl: qcom: Add SM8550 pinctrl
On 22-12-30 21:44:58, Abel Vesa wrote:
> Add device tree binding Documentation details for Qualcomm SM8550
> TLMM device
>
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
Forgot Krzysztof's R-b tag.
I'll resend.
> ---
> .../bindings/pinctrl/qcom,sm8550-tlmm.yaml | 163 ++++++++++++++++++
> 1 file changed, 163 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml
> new file mode 100644
> index 000000000000..a457425ba112
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml
> @@ -0,0 +1,163 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. SM8550 TLMM block
> +
> +maintainers:
> + - Abel Vesa <abel.vesa@...aro.org>
> +
> +description:
> + Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC.
> +
> +allOf:
> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,sm8550-tlmm
> +
> + reg:
> + maxItems: 1
> +
> + interrupts: true
> + interrupt-controller: true
> + "#interrupt-cells": true
> + gpio-controller: true
> +
> + gpio-reserved-ranges:
> + minItems: 1
> + maxItems: 105
> +
> + gpio-line-names:
> + maxItems: 210
> +
> + "#gpio-cells": true
> + gpio-ranges: true
> + wakeup-parent: true
> +
> +patternProperties:
> + "-state$":
> + oneOf:
> + - $ref: "#/$defs/qcom-sm8550-tlmm-state"
> + - patternProperties:
> + "-pins$":
> + $ref: "#/$defs/qcom-sm8550-tlmm-state"
> + additionalProperties: false
> +
> +$defs:
> + qcom-sm8550-tlmm-state:
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
> +
> + properties:
> + pins:
> + description:
> + List of gpio pins affected by the properties specified in this
> + subnode.
> + items:
> + oneOf:
> + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
> + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
> + minItems: 1
> + maxItems: 36
> +
> + function:
> + description:
> + Specify the alternative function to be configured for the specified
> + pins.
> + enum: [ aon_cci, aoss_cti, atest_char, atest_usb,
> + audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk,
> + cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl,
> + cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx,
> + coex_uart1_tx, coex_uart2_rx, coex_uart2_tx,
> + cri_trng, dbg_out_clk, ddr_bist_complete,
> + ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
> + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot,
> + gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0,
> + i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
> + i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
> + i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck,
> + i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws,
> + ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out,
> + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
> + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
> + pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,
> + pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
> + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
> + qlink0_enable, qlink0_request, qlink0_wmss,
> + qlink1_enable, qlink1_request, qlink1_wmss,
> + qlink2_enable, qlink2_request, qlink2_wmss,
> + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs,
> + qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
> + qup1_se5, qup1_se6, qup1_se7, qup2_se0,
> + qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira,
> + qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb,
> + qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1,
> + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
> + qup2_se7, sd_write_protect, sdc40, sdc41, sdc42,
> + sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
> + tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
> + tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
> + tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3,
> + uim0_clk, uim0_data, uim0_present, uim0_reset,
> + uim1_clk, uim1_data, uim1_present, uim1_reset,
> + usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ]
> +
> + bias-disable: true
> + bias-pull-down: true
> + bias-pull-up: true
> + drive-strength: true
> + input-enable: true
> + output-high: true
> + output-low: true
> +
> + required:
> + - pins
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + tlmm: pinctrl@...0000 {
> + compatible = "qcom,sm8550-tlmm";
> + reg = <0x0f100000 0x300000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 211>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +
> + gpio-wo-state {
> + pins = "gpio1";
> + function = "gpio";
> + };
> +
> + uart-w-state {
> + rx-pins {
> + pins = "gpio26";
> + function = "qup2_se7";
> + bias-pull-up;
> + };
> +
> + tx-pins {
> + pins = "gpio27";
> + function = "qup2_se7";
> + bias-disable;
> + };
> + };
> + };
> +...
> --
> 2.34.1
>
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