linux-kernel - Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <5818a83e644eb9c868d4cf65117983e08ba1c17f.camel@icenowy.me>
Date:   Sat, 31 Dec 2022 12:36:04 +0800
From:   Icenowy Zheng <uwu@...nowy.me>
To:     Sergey Matyukevich <geomatsi@...il.com>
Cc:     Guo Ren <guoren@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Heiko Stuebner <heiko@...ech.de>,
        Nathan Chancellor <nathan@...nel.org>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding

在 2022-12-31星期六的 01:12 +0300，Sergey Matyukevich写道：
> > > The dcache.cva encoding shown in the comments are wrong, it's for
> > > dcache.cval1 (which is restricted to L1) instead.
> > > 
> > > Fix this in the comment and in the hardcoded instruction.
> > > 
> > > Signed-off-by: Icenowy Zheng <uwu@...nowy.me>
> > > ---
> > > The code is tested on a LiteX SoC with OpenC906 core, and it
> > > successfully boots to Systemd on a SD card connected to
> > > LiteSDCard.
> > > 
> > > This change should be not noticable on C906, but on multi-core
> > > C910
> > > cluster it should fixes something. Unfortunately TH1520 seems to
> > > be not
> > > so ready to test mainline patches on.
> > > 
> > >  arch/riscv/include/asm/errata_list.h | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/arch/riscv/include/asm/errata_list.h
> > > b/arch/riscv/include/asm/errata_list.h
> > > index 4180312d2a70..605800bd390e 100644
> > > --- a/arch/riscv/include/asm/errata_list.h
> > > +++ b/arch/riscv/include/asm/errata_list.h
> > > @@ -102,7 +102,7 @@ asm
> > > volatile(ALTERNATIVE(                                           \
> > >   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > >   *   0000001    01001      rs1       000      00000  0001011
> > >   * dcache.cva rs1 (clean, virtual address)
> > > - *   0000001    00100      rs1       000      00000  0001011
> > > + *   0000001    00101      rs1       000      00000  0001011
> > >   *
> > >   * dcache.cipa rs1 (clean then invalidate, physical address)
> > >   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > > @@ -115,7 +115,7 @@ asm
> > > volatile(ALTERNATIVE(                                           \
> > >   *   0000000    11001     00000      000      00000  0001011
> > >   */
> > >  #define THEAD_inval_A0 ".long 0x0265000b"
> > > -#define THEAD_clean_A0 ".long 0x0245000b"
> > > +#define THEAD_clean_A0 ".long 0x0255000b"
> > >  #define THEAD_flush_A0 ".long 0x0275000b"
> > >  #define THEAD_SYNC_S   ".long 0x0190000b"
> 
> Nice catch ! I experimented with T-Head RVB-ICE board on the up-to-
> date
> upstream kernel, using device tree and some other bits from the
> vendor
> kernel [1]. Without this patch, emmc on this board does not work
> since
> noncoherent dma sync operations use incorrect 'clean' instruction.
> Applying this patch fixes emmc operations, so

Thanks for testing on C910! I don't think this patch will make a
significant difference on C906, so it's valuable!

> 
> Tested-by: Sergey Matyukevich <sergey.matyukevich@...tacore.com>
> 
> [1] https://github.com/T-head-Semi/linux/tree/linux-5.10.4
> 
> Regards,
> Sergey