linux-kernel - [PATCH v2] PCI: mt7621: Sleep a bit after power on the PCIs phy ports

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Date:   Sat, 31 Dec 2022 08:40:41 +0100
From:   Sergio Paracuellos <sergio.paracuellos@...il.com>
To:     linux-pci@...r.kernel.org
Cc:     bhelgaas@...gle.com, lpieralisi@...nel.org, robh@...nel.org,
        kw@...ux.com, matthias.bgg@...il.com, linux-kernel@...r.kernel.org
Subject: [PATCH v2] PCI: mt7621: Sleep a bit after power on the PCIs phy ports

Some devices like ZBT WE1326 and ZBT WF3526-P and some Netgear models need
to sleep a bit after call to mt7621_pcie_init_port() driver function to get
into reliable boots for both warm and hard resets. The needed time for these
devices to always detect the ports seems to be from 75 to 100 milliseconds.
There is no datasheet or something similar to really understand why this
extra time is needed in these devices but not in most of the boards which
use mt7621 SoC. This issue has been reported by openWRT community and the
complete discussion is in [0]. The selected time of 100 milliseconds has
been also tested in these devices ending up in an always working platform.
Hence, properly add the extra 100 milliseconds msleep() function call to make
also these devices work.

[0]: https://github.com/openwrt/openwrt/pull/11220

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@...il.com>
---
Hi Bjorn / Lorenzo,

As per Lorenzo comments in v1[0] here it is the patch with changes in commit
message and introducing a new definition for this needed extra delay time.
I wish you the best new year for you both.

Changes in v2:
- Add a new define 'INIT_PORTS_DELAY_MS' avoiding to reuse 'PERST_DELAY_MS'.
- Rewrite commit message and add a link to openWRT discussion.

Previous patch lore link:
[0]: https://lore.kernel.org/lkml/20221209071703.2891714-1-sergio.paracuellos@gmail.com/T/

Thanks,
    Sergio Paracuellos

 drivers/pci/controller/pcie-mt7621.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/controller/pcie-mt7621.c b/drivers/pci/controller/pcie-mt7621.c
index ee7aad09d627..63a5f4463a9f 100644
--- a/drivers/pci/controller/pcie-mt7621.c
+++ b/drivers/pci/controller/pcie-mt7621.c
@@ -60,6 +60,7 @@
 #define PCIE_PORT_LINKUP		BIT(0)
 #define PCIE_PORT_CNT			3

+#define INIT_PORTS_DELAY_MS		100
 #define PERST_DELAY_MS			100

 /**
@@ -369,6 +370,7 @@ static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
 		}
 	}

+	msleep(INIT_PORTS_DELAY_MS);
 	mt7621_pcie_reset_ep_deassert(pcie);

 	tmp = NULL;
-- 
2.25.1