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Message-ID: <20230102064844.31306-1-mkumard@nvidia.com>
Date:   Mon, 2 Jan 2023 12:18:44 +0530
From:   Mohan Kumar <mkumard@...dia.com>
To:     <ldewangan@...dia.com>, <jonathanh@...dia.com>, <vkoul@...nel.org>,
        <thierry.reding@...il.com>
CC:     <dmaengine@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, Mohan Kumar <mkumard@...dia.com>,
        <stable@...r.kernel.org>
Subject: [PATCH v2] dmaengine: tegra210-adma: fix global intr clear

The current global interrupt clear programming register offset
was not correct. Fix the programming with right offset

Fixes: ded1f3db4cd6 ("dmaengine: tegra210-adma: prepare for supporting newer Tegra chips")
Cc: stable@...r.kernel.org
Signed-off-by: Mohan Kumar <mkumard@...dia.com>
---
 drivers/dma/tegra210-adma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
index ae39b52012b2..79da93cc77b6 100644
--- a/drivers/dma/tegra210-adma.c
+++ b/drivers/dma/tegra210-adma.c
@@ -221,7 +221,7 @@ static int tegra_adma_init(struct tegra_adma *tdma)
 	int ret;
 
 	/* Clear any interrupts */
-	tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
+	tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1);
 
 	/* Assert soft reset */
 	tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
-- 
2.17.1

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