linux-kernel - Re: RFC on drivers/memory vs drivers/edac memory mapping for DDR Controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <567f14ef-7940-25c5-9323-c673b98e585a@amazon.com>
Date:   Mon, 2 Jan 2023 18:21:27 +0200
From:   "Shenhar, Talel" <talel@...zon.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        <bp@...en8.de>
CC:     <talelshenhar@...il.com>, <shellykz@...zon.com>,
        <linux-edac@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: RFC on drivers/memory vs drivers/edac memory mapping for DDR Controller


On 1/2/2023 3:59 PM, Krzysztof Kozlowski wrote:
>
> On 02/01/2023 14:44, Shenhar, Talel wrote:
>> On 1/2/2023 2:47 PM, Krzysztof Kozlowski wrote:
>>>
>>> On 02/01/2023 13:17, Shenhar, Talel wrote:
>>>
>>>> Things we had in mind:
>>>> 1) map more specific region to avoid conflict (we don't need the same
>>>> registers on both entity so if we do very specific multiple mapping this
>>>> shall be resolved)
>>>> 2) use other kernel API for mapping that doesn't do request_mem_region
>>>> (or use the reserve only for one of them)
>>>> 3) have single driver (edac mc) handle also the refresh rate
>>>> 4) export edac_mc.h and have the drivers/memory have all the needed code
>>>> to do both edac and refresh rate under drivers/memory
>>> None of these address the core problem - possibly inaccurate hardware
>>> description...
>> Can you elaborate on this inaccurate hardware description?
> I explained - using same IO address suggests you used Linux driver
> structure in your hardware description. I assume we talk here about
> Devicetree. If not, that's quite different case... then I guess ACPI,
> which I do not care - I am not it's maintainer.
>
>> Also, I'd like to write down my understanding of your response from above:
>>
>> it seems you see as possible solution both using different API that
>> allow overlapping (solution 2) and also for splitting the IO address
>> space to finer pieces to achieve full HW description (solution 1)
> No. Sorry, we probably talk about two different things.
>
> You started writing that you have a hardware described as one IO address
> space and now have a problem developing drivers for it.
>
> The driver model for this is entirely different problem than problem of
> accurate hardware description. Whether you described HW correct or not,
> I don't know. You did not provide any details here, like DTS or bindings
> (if we talk about Devicetree).
>
> Having multiple drivers using similar resources is already solved many
> times (MFD, syscon).
>
> Whether the solution is correct or not is one more (third) topic: poking
> to same IO address space from two different drivers is error-prone. This
> one is solvable with splitting IO address space.
>
> Best regards,
> Krzysztof


You are right.

Let me elaborate on this.

We will write down the hardware description via device tree.

Then we will write the driver which will honor that binding.

So the question is what is the best practice there assuming there is no 
shared registers however there is overlapping.

e.g. the EDAC driver needs register 0,1,2,4,5 and refresh-rate needs 
register 3.

If we would only have EDAC driver than we would do IO address mapping 
from 0 with size 5 (not caring mapping register 3 even that its not used).

However, with the other driver (refresh rate) that need register 3 we am 
facing a problem.

So looking for the best solution here.

I don't think this is a problem that is specific to drivers/edac and to 
drivers/memory, however, due to the nature of those two libraries this 
conflict is more expected.


>