linux-kernel - Re: [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2

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Message-ID: <5c5716e5-b2ff-67cd-b608-4eeffa7e04bc@oracle.com>
Date:   Tue, 3 Jan 2023 11:52:12 +0000
From:   John Garry <john.g.garry@...cle.com>
To:     Jing Zhang <renyu.zj@...ux.alibaba.com>,
        Ian Rogers <irogers@...gle.com>,
        Xing Zhengjun <zhengjun.xing@...ux.intel.com>,
        Will Deacon <will@...nel.org>,
        James Clark <james.clark@....com>,
        Mike Leach <mike.leach@...aro.org>,
        Leo Yan <leo.yan@...aro.org>
Cc:     linux-arm-kernel@...ts.infradead.org,
        linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Andrew Kilroy <andrew.kilroy@....com>,
        Shuai Xue <xueshuai@...ux.alibaba.com>,
        Zhuo Song <zhuo.song@...ux.alibaba.com>
Subject: Re: [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 metrics
 for neoverse-n2

On 03/01/2023 11:39, Jing Zhang wrote:
> The formula of topdown L1 on neoverse-n2 is from ARM sbsa7.0 platform
> design document [0], D37-38.

I think that I mentioned this before - if the these metrics are coming 
from an sbsa doc, then they are standard. As such, we can make them 
"arch std events" and put them in a common json such as sbsa.json, so 
that other cores may reuse.

You don't strictly have to do do this now, but it would be better.

Thanks,
John

> 
> However, due to the wrong count of stall_slot and stall_slot_frontend on
> neoverse-n2, the real stall_slot and real stall_slot_frontend need to
> subtract cpu_cycles,  so correct the expression of topdown metrics.
> Reference from ARM neoverse-n2 errata notice [1], D117.
> 
> Since neoverse-n2 does not yet support topdown L2, metricgroups such as
> Cache, TLB, Branch, InstructionsMix, and PEutilization will be added to
> further analysis of performance bottlenecks in the following patches.
> Reference from ARM PMU guide [2][3].