[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <add4e548-c7cd-741d-90e5-5c7c9ec7284f@linaro.org>
Date: Tue, 3 Jan 2023 15:24:26 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: "Shenhar, Talel" <talel@...zon.com>, bp@...en8.de
Cc: talelshenhar@...il.com, shellykz@...zon.com,
linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: RFC on drivers/memory vs drivers/edac memory mapping for DDR
Controller
On 03/01/2023 14:47, Shenhar, Talel wrote:
> So how would you have the DT described and how would driver/s look like
> for cases that the unit registers are split interchangeably?
>
>>
>> You did not Cc relevant here mailing addresses (DT and Rob), so this
>> discussion might miss their feedback.
>>
>> How the drivers map IO address space is independent question and should
>> not determine the hardware description. You want to say that hardware
>> changes depending on OS? One OS means hardware is like that and on other
>> OS it's different?
BTW, you nicely skipped points of my email which are a bit
inconvenient,e.g. how you want to tie DTS and bindings to one specific
driver implementation and ignore the rest...
Best regards,
Krzysztof
Powered by blists - more mailing lists